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74ALVCH16240TX PDF预览

74ALVCH16240TX

更新时间: 2024-11-20 23:24:07
品牌 Logo 应用领域
飞兆/仙童 - FAIRCHILD 驱动
页数 文件大小 规格书
6页 88K
描述
BUFFER/DRIVER|QUAD|4-BIT|AVC/ALVC-CMOS|TSSOP|48PIN|PLASTIC

74ALVCH16240TX 技术参数

是否Rohs认证: 不符合生命周期:Obsolete
零件包装代码:TSSOP包装说明:TSSOP, TSSOP48,.3,20
针数:48Reach Compliance Code:not_compliant
风险等级:5.2控制类型:ENABLE LOW
系列:ALVC/VCX/AJESD-30 代码:R-PDSO-G48
JESD-609代码:e0长度:12.5 mm
逻辑集成电路类型:BUS DRIVER最大I(ol):0.024 A
湿度敏感等级:2位数:4
功能数量:4端口数量:2
端子数量:48最高工作温度:85 °C
最低工作温度:-40 °C输出特性:3-STATE
输出极性:INVERTED封装主体材料:PLASTIC/EPOXY
封装代码:TSSOP封装等效代码:TSSOP48,.3,20
封装形状:RECTANGULAR封装形式:SMALL OUTLINE, THIN PROFILE, SHRINK PITCH
包装方法:TAPE AND REEL电源:3.3 V
Prop。Delay @ Nom-Sup:3.9 ns传播延迟(tpd):6 ns
认证状态:Not Qualified座面最大高度:1.2 mm
子类别:Bus Driver/Transceivers最大供电电压 (Vsup):3.6 V
最小供电电压 (Vsup):1.65 V标称供电电压 (Vsup):1.8 V
表面贴装:YES技术:CMOS
温度等级:INDUSTRIAL端子面层:Tin/Lead (Sn85Pb15)
端子形式:GULL WING端子节距:0.5 mm
端子位置:DUAL宽度:6.1 mm
Base Number Matches:1

74ALVCH16240TX 数据手册

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September 2001  
Revised February 2002  
74ALVCH16240  
Low Voltage 16-Bit Inverting Buffer/Line Driver  
with Bushold  
General Description  
The ALVCH16240 contains sixteen inverting buffers with  
Features  
3-STATE outputs to be employed as  
a memory and  
1.65V to 3.6V VCC supply operation  
address driver, clock driver, or bus oriented transmitter/  
receiver. The device is nibble (4-bit) controlled. Each nibble  
has separate 3-STATE control inputs which can be shorted  
together for full 16-bit operation.  
3.6V tolerant control inputs and outputs  
Bushold on data inputs eliminates the need for external  
pull-up/pull-down resistors  
The ALVCH16240 data inputs include active bushold cir-  
cuitry, eliminating the need for external pull-up resistors to  
hold unused or floating inputs at a valid logic level.  
tPD  
3.9 ns max for 3.0V to 3.6V VCC  
5.3 ns max for 2.3V to 2.7V VCC  
6.0 ns max for 1.65V to 1.95V VCC  
The 74ALVCH16240 is designed for low voltage (1.65V to  
3.6V) VCC applications with output capability up to 3.6V.  
The 74ALVCH16240 is fabricated with an advanced CMOS  
technology to achieve high speed operation while maintain-  
ing low CMOS power dissipation.  
Uses patented noise/EMI reduction circuitry  
Latch-up conforms to JEDEC JED78  
ESD performance:  
Human body model > 2000V  
Machine model > 200V  
Ordering Code:  
Package  
Order Number  
Package Descriptions  
Number  
74ALVCH16240T  
MTD48  
48-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 6.1mm Wide  
Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code.  
Logic Symbol  
Pin Descriptions  
Pin Names  
Description  
OEn  
Output Enable Input (Active LOW)  
Bushold Inputs  
I0I15  
O0O15  
Outputs  
© 2002 Fairchild Semiconductor Corporation  
DS500629  
www.fairchildsemi.com  

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