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74ALVCH162374TTR PDF预览

74ALVCH162374TTR

更新时间： 2024-11-05 14:47:03
品牌 Logo 应用领域
意法半导体 - STMICROELECTRONICS 驱动光电二极管输出元件逻辑集成电路触发器
页数 文件大小 规格书
10页 236K
描述
ALVC/VCX/A SERIES, DUAL 8-BIT DRIVER, TRUE OUTPUT, PDSO48, TSSOP-48

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中文翻译

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74ALVCH162374TTR 技术参数

生命周期：Obsolete零件包装代码：TSSOP
包装说明：TSSOP-48针数：48
Reach Compliance Code：compliantHTS代码：8542.39.00.01
风险等级：5.48Is Samacsys：N
系列：ALVC/VCX/AJESD-30 代码：R-PDSO-G48
长度：12.5 mm负载电容（CL）：50 pF
逻辑集成电路类型：BUS DRIVER最大频率@ Nom-Sup：300000000 Hz
最大I（ol）：0.012 A位数：8
功能数量：2端口数量：2
端子数量：48最高工作温度：125 °C
最低工作温度：-55 °C输出特性：3-STATE WITH SERIES RESISTOR
输出极性：TRUE封装主体材料：PLASTIC/EPOXY
封装代码：TSSOP封装等效代码：TSSOP48,.3,20
封装形状：RECTANGULAR封装形式：SMALL OUTLINE, THIN PROFILE, SHRINK PITCH
包装方法：TAPE AND REEL电源：3.3 V
Prop。Delay @ Nom-Sup：4.6 ns传播延迟（tpd）：6.5 ns
认证状态：Not Qualified座面最大高度：1.2 mm
子类别：FF/Latches最大供电电压 (Vsup)：3.6 V
最小供电电压 (Vsup)：1.65 V标称供电电压 (Vsup)：2.7 V
表面贴装：YES技术：CMOS
温度等级：MILITARY端子形式：GULL WING
端子节距：0.5 mm端子位置：DUAL
触发器类型：POSITIVE EDGE宽度：6.1 mm
Base Number Matches：1

74ALVCH162374TTR 数据手册

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74ALVCH162374  
LOW VOLTAGE CMOS 16-BIT D-TYPE FLIP-FLOP (3-STATE)  
WITH 3.6V TOLERANT INPUTS AND OUTPUTS  
PRELIMINARY DATA  
■
■
3.6V TOLERANT INPUTS AND OUTPUTS  
HIGH SPEED :  
t
t
t
= 4.6 ns (MAX.) at V = 3.0 to 3.6V  
PD  
PD  
PD  
CC  
= 5.4 ns (MAX.) at V = 2.3 to 2.7V  
CC  
= 6.5 ns (MAX.) at V = 1.65V  
CC  
■
■
POWER DOWN PROTECTION ON INPUTS  
AND OUTPUTS  
SYMMETRICAL OUTPUT IMPEDANCE:  
TSSOP  
|I | = I = 24mA (MIN) at V = 3.0V  
OH  
OL  
CC  
|I | = I = 18mA (MIN) at V = 2.3V  
OH  
OL  
CC  
ORDER CODES  
PACKAGE  
|I | = I = 4mA (MIN) at V = 1.65V  
OH  
OL  
CC  
■
■
■
BUS HOLD PROVIDED ON DATA INPUTS  
26Ω SERIE RESISTORS IN OUTPUTS  
OPERATING VOLTAGE RANGE:  
TUBE  
T & R  
TSSOP  
74ALVCH162374T  
V
(OPR) = 1.65V to 3.6V  
CC  
PIN CONNECTION  
■
■
■
PIN AND FUNCTION COMPATIBLE WITH  
74 SERIES 16374  
LATCH-UP PERFORMANCE EXCEEDS  
300mA (JESD 17)  
ESD PERFORMANCE:  
HBM > 2000V (MIL STD 883 method 3015);  
MM > 200V  
DESCRIPTION  
The 74ALVCH162374 is a low voltage CMOS 16  
BIT D-TYPE LATCH with 3 STATE OUTPUTS  
NON INVERTING fabricated with sub-micron  
2
silicon gate and five-layer metal wiring C MOS  
technology. It is ideal for low power and very high  
speed 1.65 to 3.6V applications; it can be  
interfaced to 3.6V signal environment for both  
inputs and outputs.  
These flip-flops are controlled by two clock inputs  
(nCK) and two output enable inputs (nOE).  
On the positive transition of the (nCK), the nQ  
outputs will be set to the logic state that were  
setup at the nD inputs.  
While the (nOE) input is low, the outputs (nQ) will  
be in a normal state (HIGH or LOW logic level)  
and while high level the outputs will be in a high  
impedance state.  
Any output control does not affect the internal  
operation of flip flops; that is, the old data can be  
retained or the new data can be entered even  
while the outputs are off.The device circuits is  
including 26Ω series resistance in the outputs.  
These resistors permit to reduce line noise in high  
speed applications.  
All inputs and outputs are equipped with  
protection circuits against static discharge, giving  
them 2KV ESD immunity and transient excess  
voltage.  
October 2002  
1/10  
This is preliminary information on a new product now in development are or undergoing evaluation. Details subject to change without notice.  
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