5秒后页面跳转
捷配首页

Datasheet > 74ALVCH162260GRE4
74ALVCH162260GRE4 PDF预览

74ALVCH162260GRE4

更新时间： 2024-11-18 14:49:19
品牌 Logo 应用领域
德州仪器 - TI 光电二极管逻辑集成电路
页数 文件大小 规格书
14页 181K
描述
12-Bit To 24-Bit Multiplexed D-Type Latch With 3-State Outputs 56-TSSOP -40 to 85

阅读下载

中文翻译

获取价格

74ALVCH162260GRE4 技术参数

是否无铅：不含铅是否Rohs认证：符合
生命周期：Obsolete零件包装代码：TSSOP
包装说明：TSSOP, TSSOP56,.3,20针数：56
Reach Compliance Code：unknownHTS代码：8542.39.00.01
风险等级：5.71Is Samacsys：N
系列：ALVC/VCX/AJESD-30 代码：R-PDSO-G56
JESD-609代码：e4长度：14 mm
逻辑集成电路类型：MULTIPLEXER AND DEMUX/DECODER湿度敏感等级：1
功能数量：2输入次数：12
输出次数：2端子数量：56
最高工作温度：85 °C最低工作温度：-40 °C
输出特性：3-STATE WITH SERIES RESISTOR输出极性：TRUE
封装主体材料：PLASTIC/EPOXY封装代码：TSSOP
封装等效代码：TSSOP56,.3,20封装形状：RECTANGULAR
封装形式：SMALL OUTLINE, THIN PROFILE, SHRINK PITCH峰值回流温度（摄氏度）：260
电源：3.3 V传播延迟（tpd）：6.1 ns
认证状态：Not Qualified座面最大高度：1.2 mm
子类别：Other Logic ICs最大供电电压 (Vsup)：3.6 V
最小供电电压 (Vsup)：1.65 V标称供电电压 (Vsup)：1.8 V
表面贴装：YES技术：CMOS
温度等级：INDUSTRIAL端子面层：Nickel/Palladium/Gold (Ni/Pd/Au)
端子形式：GULL WING端子节距：0.5 mm
端子位置：DUAL处于峰值回流温度下的最长时间：NOT SPECIFIED
宽度：6.1 mmBase Number Matches：1

74ALVCH162260GRE4 数据手册

 浏览型号74ALVCH162260GRE4的Datasheet PDF文件第2页浏览型号74ALVCH162260GRE4的Datasheet PDF文件第3页浏览型号74ALVCH162260GRE4的Datasheet PDF文件第4页浏览型号74ALVCH162260GRE4的Datasheet PDF文件第5页浏览型号74ALVCH162260GRE4的Datasheet PDF文件第6页浏览型号74ALVCH162260GRE4的Datasheet PDF文件第7页 
SN74ALVCH162260  
12-BIT TO 24-BIT MULTIPLEXED D-TYPE LATCH  
WITH 3-STATE OUTPUTS  
www.ti.com  
SCAS570I–MARCH 1996–REVISED AUGUST 2004  
FEATURES  
DGG OR DL PACKAGE  
(TOP VIEW)  
•
•
•
Member of the Texas Instruments Widebus™  
Family  
1
56  
55  
54  
53  
52  
51  
50  
49  
48  
47  
46  
45  
44  
43  
42  
41  
40  
39  
38  
37  
36  
35  
34  
33  
32  
31  
30  
29  
OEA  
LE1B  
2B3  
OE2B  
LEA2B  
2B4  
EPIC™ (Enhanced-Performance Implanted  
CMOS) Submicron Process  
2
3
B-Port Outputs Have Equivalent 26-Ω Series  
Resistors, So No External Resistors Are  
Required  
4
GND  
2B2  
GND  
2B5  
5
6
2B1  
2B6  
•
ESD Protection Exceeds 2000 V Per  
7
V
CC  
V
CC  
MIL-STD-883, Method 3015; Exceeds 200 V  
Using Machine Model (C = 200 pF, R = 0)  
8
A1  
A2  
2B7  
2B8  
9
•
•
•
Latch-Up Performance Exceeds 250 mA Per  
JESD 17  
10  
11  
12  
13  
14  
15  
16  
17  
18  
19  
20  
21  
22  
23  
24  
25  
26  
27  
28  
A3  
GND  
A4  
2B9  
GND  
2B10  
2B11  
2B12  
1B12  
1B11  
1B10  
GND  
1B9  
Bus Hold on Data Inputs Eliminates the Need  
for External Pullup/Pulldown Resistors  
A5  
Package Options Include Thin-Shrink  
Small-Outline (DGG) and Plastic Shrink  
Small-Outline (DL) Packages  
A6  
A7  
A8  
A9  
GND  
A10  
A11  
A12  
NOTE:  
For tape-and-reel order entry: The DGGR package is  
abbreviated to GR.  
DESCRIPTION  
1B8  
1B7  
This 12-bit to 24-bit multiplexed D-type latch is  
designed for 1.65-V to 3.6-V VCC operation.  
V
CC  
V
CC  
1B1  
1B2  
1B6  
1B5  
The SN74ALVCH162260 is used in applications in  
which two separate data paths must be multiplexed  
onto, or demultiplexed from, a single data path.  
Typical applications include multiplexing and/or  
demultiplexing address and data information in  
microprocessor or bus-interface applications. This  
device also is useful in memory-interleaving  
applications.  
GND  
1B3  
LE2B  
SEL  
GND  
1B4  
LEA1B  
OE1B  
Three 12-bit I/O ports (A1-A12, 1B1-1B12, and 2B1-2B12) are available for address and/or data transfer. The  
output-enable (OE1B, OE2B, and OEA) inputs control the bus transceiver functions. The OE1B and OE2B  
control signals also allow bank control in the A-to-B direction.  
Address and/or data information can be stored using the internal storage latches. The latch-enable (LE1B, LE2B,  
LEA1B, and LEA2B) inputs are used to control data storage. When the latch-enable input is high, the latch is  
transparent. When the latch-enable input goes low, the data present at the inputs is latched and remains latched  
until the latch-enable input is returned high.  
The B outputs, which are designed to sink up to 12 mA, include equivalent 26-Ω resistors to reduce overshoot  
and undershoot.  
To ensure the high-impedance state during power up or power down, OE should be tied to VCC through a pullup  
resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.  
Active bus-hold circuitry is provided to hold unused or floating data inputs at a valid logic level.  
The SN74ALVCH162260 is characterized for operation from -40°C to 85°C.  
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas  
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.  
Widebus, EPIC are trademarks of Texas Instruments.  
PRODUCTION DATA information is current as of publication date.  
Copyright © 1996–2004, Texas Instruments Incorporated  
Products conform to specifications per the terms of the Texas  
Instruments standard warranty. Production processing does not  
necessarily include testing of all parameters.  
1234567...14

中文翻译

下载PDF

74ALVCH162260GRE4 替代型号

型号 品牌 替代类型 描述 数据表
SN74ALVCH162260GR TI

类似代替

 12-BIT TO 24-BIT MULTIPLEXED D-TYPE LATCH WITH 3-STATE OUTPUTS
SN74ALVCH162260DGGR TI

类似代替

 12-BIT TO 24-BIT MULTIPLEXED D-TYPE LATCH WITH 3-STATE OUTPUTS

与74ALVCH162260GRE4相关器件

型号 品牌 获取价格 描述 数据表
74ALVCH162268GRE4 TI

获取价格

 		ALVC/VCX/A SERIES, 12-BIT EXCHANGER, TRUE OUTPUT, PDSO56, GREEN, PLASTIC, TSSOP-56
74ALVCH162268ZQLR TI

获取价格

 		12-BIT TO 24-BIT REGISTERED BUS EXCHANGER WITH 3-STATE OUTPUTS
74ALVCH162373 FAIRCHILD

获取价格

 		Low Voltage 16-Bit Transparent Latch with Bus
74ALVCH162373DLG4 TI

获取价格

 		16-BIT TRANSPARENT D-TYPE LATCH WITH 3-STATE OUTPUTS
74ALVCH162373GRE4 TI

获取价格

 		16-BIT TRANSPARENT D-TYPE LATCH WITH 3-STATE OUTPUTS
74ALVCH162373GRG4 TI

获取价格

 		16-BIT TRANSPARENT D-TYPE LATCH WITH 3-STATE OUTPUTS
74ALVCH162373LRG4 TI

获取价格

 		16-BIT TRANSPARENT D-TYPE LATCH WITH 3-STATE OUTPUTS
74ALVCH162373PA IDT

获取价格

 		Bus Driver, ALVC/VCX/A Series, 2-Func, 8-Bit, True Output, CMOS, PDSO48, TSSOP-48
74ALVCH162373PAG IDT

获取价格

 		3.3V CMOS 16-BIT TRANS- PARENT D-TYPE LATCH
74ALVCH162373PAG8 IDT

获取价格

 		3.3V CMOS 16-BIT TRANS- PARENT D-TYPE LATCH

与74ALVCH162260GRE4相关文章

您还可以找


热门产品
PCB打样/小批量
铝基板
BOM智能配单
PCBA制造
钣金
精密CNC
模具注塑
薄膜开关
精选活动
PCBA打样特惠
四六层板品质升级
铝基板品质升级
一体化电子制造
DFM下载
服务支持
企业认证
产品展示
工厂展示
工艺能力
积分商城
关于捷配
捷配简介
企业文化
公司动态
人才招聘
联系我们
帮助中心
下单流程
付款流程
开票流程
常见问题
全球PCB制造服务专线 400-613-0088

工作时间：9:00-21:00

CEO邮箱：ceo@jiepei.com

投诉邮箱：tousu@jiepei.com

捷配网-微信公众号 微信公众号
捷配网-微信公众号 抖音公众号
资质认证：
合作快递：
支付方式：
Copyright © 2024 Jiepei.com Inc. All Rights Reserved. 版权所有:杭州捷配信息科技有限公司 浙公网安备 33010502006866号 浙ICP备10014259号-119 营业执照ICP证