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SN74ALVCH162260GR PDF预览

SN74ALVCH162260GR

更新时间： 2024-11-19 02:58:39
品牌 Logo 应用领域
德州仪器 - TI 光电二极管输出元件逻辑集成电路
页数 文件大小 规格书
11页 152K
描述
12-BIT TO 24-BIT MULTIPLEXED D-TYPE LATCH WITH 3-STATE OUTPUTS

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中文翻译

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SN74ALVCH162260GR 技术参数

是否无铅： 不含铅是否Rohs认证： 符合
生命周期：Active零件包装代码：TSSOP
包装说明：TSSOP, TSSOP56,.3,20针数：56
Reach Compliance Code：compliantECCN代码：EAR99
HTS代码：8542.39.00.01Factory Lead Time：1 week
风险等级：1.44系列：ALVC/VCX/A
JESD-30 代码：R-PDSO-G56JESD-609代码：e4
长度：14 mm负载电容（CL）：50 pF
逻辑集成电路类型：MULTIPLEXER AND DEMUX/DECODER最大I（ol）：0.012 A
湿度敏感等级：1位数：12
功能数量：2输入次数：12
输出次数：2端子数量：56
最高工作温度：85 °C最低工作温度：-40 °C
输出特性：3-STATE WITH SERIES RESISTOR输出极性：TRUE
封装主体材料：PLASTIC/EPOXY封装代码：TSSOP
封装等效代码：TSSOP56,.3,20封装形状：RECTANGULAR
封装形式：SMALL OUTLINE, THIN PROFILE, SHRINK PITCH包装方法：TR
峰值回流温度（摄氏度）：260电源：3.3 V
最大电源电流（ICC）：0.04 mAProp。Delay @ Nom-Sup：5.9 ns
传播延迟（tpd）：6.1 ns认证状态：Not Qualified
座面最大高度：1.2 mm子类别：Other Logic ICs
最大供电电压 (Vsup)：3.6 V最小供电电压 (Vsup)：1.65 V
标称供电电压 (Vsup)：1.8 V表面贴装：YES
技术：CMOS温度等级：INDUSTRIAL
端子面层：Nickel/Palladium/Gold (Ni/Pd/Au)端子形式：GULL WING
端子节距：0.5 mm端子位置：DUAL
处于峰值回流温度下的最长时间：NOT SPECIFIED宽度：6.1 mm
Base Number Matches：1

SN74ALVCH162260GR 数据手册

 浏览型号SN74ALVCH162260GR的Datasheet PDF文件第2页浏览型号SN74ALVCH162260GR的Datasheet PDF文件第3页浏览型号SN74ALVCH162260GR的Datasheet PDF文件第4页浏览型号SN74ALVCH162260GR的Datasheet PDF文件第5页浏览型号SN74ALVCH162260GR的Datasheet PDF文件第6页浏览型号SN74ALVCH162260GR的Datasheet PDF文件第7页 
SN74ALVCH162260  
12-BIT TO 24-BIT MULTIPLEXED D-TYPE LATCH  
WITH 3-STATE OUTPUTS  
SCAS570H – MARCH 1996 – REVISED JUNE 1999  
DGG OR DL PACKAGE  
(TOP VIEW)  
Member of the Texas Instruments  
Widebus Family  
EPIC (Enhanced-Performance Implanted  
CMOS) Submicron Process  
OEA  
LE1B  
2B3  
GND  
2B2  
OE2B  
LEA2B  
2B4  
GND  
2B5  
1
56  
55  
54  
53  
52  
51  
50  
49  
48  
47  
46  
45  
44  
43  
42  
41  
40  
39  
38  
37  
36  
35  
34  
33  
32  
31  
30  
29  
2
B-Port Outputs Have Equivalent 26-Ω  
Series Resistors, So No External Resistors  
Are Required  
3
4
5
ESD Protection Exceeds 2000 V Per  
MIL-STD-883, Method 3015; Exceeds 200 V  
Using Machine Model (C = 200 pF, R = 0)  
2B1  
2B6  
6
V
V
7
CC  
CC  
A1  
A2  
A3  
GND  
A4  
A5  
A6  
A7  
A8  
2B7  
2B8  
2B9  
8
9
Latch-Up Performance Exceeds 250 mA Per  
JESD 17  
10  
11  
12  
13  
14  
15  
16  
17  
18  
19  
20  
21  
22  
23  
24  
25  
26  
27  
28  
GND  
2B10  
2B11  
2B12  
1B12  
1B11  
1B10  
GND  
1B9  
Bus Hold on Data Inputs Eliminates the  
Need for External Pullup/Pulldown  
Resistors  
Package Options Include Thin-Shrink  
Small-Outline (DGG) and Plastic Shrink  
Small-Outline (DL) Packages  
NOTE: For tape and reel order entry:  
A9  
GND  
A10  
A11  
A12  
The DGGR package is abbreviated to GR.  
description  
1B8  
1B7  
This 12-bit to 24-bit multiplexed D-type latch is  
V
V
CC  
CC  
designed for 1.65-V to 3.6-V  
operation.  
CC  
1B1  
1B2  
GND  
1B3  
LE2B  
SEL  
1B6  
1B5  
GND  
1B4  
LEA1B  
OE1B  
The SN74ALVCH162260 is used in applications  
in which two separate data paths must be  
multiplexed onto, or demultiplexed from, a single  
data path. Typical applications include  
multiplexing and/or demultiplexing address and  
data  
information  
in  
microprocessor  
or  
bus-interface applications. This device also is  
useful in memory-interleaving applications.  
Three 12-bit I/O ports (A1–A12, 1B1–1B12, and 2B1–2B12) are available for address and/or data transfer. The  
output-enable (OE1B, OE2B, and OEA) inputs control the bus transceiver functions. The OE1B and OE2B  
control signals also allow bank control in the A-to-B direction.  
Address and/or data information can be stored using the internal storage latches. The latch-enable (LE1B,  
LE2B, LEA1B, and LEA2B) inputs are used to control data storage. When the latch-enable input is high, the  
latch is transparent. When the latch-enable input goes low, the data present at the inputs is latched and remains  
latched until the latch-enable input is returned high.  
The B outputs, which are designed to sink up to 12 mA, include equivalent 26-Ω resistors to reduce overshoot  
and undershoot.  
To ensure the high-impedance state during power up or power down, OE should be tied to V through a pullup  
CC  
resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.  
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of  
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.  
EPIC and Widebus are trademarks of Texas Instruments Incorporated.  
Copyright 1999, Texas Instruments Incorporated  
PRODUCTION DATA information is current as of publication date.  
Products conform to specifications per the terms of Texas Instruments  
standard warranty. Production processing does not necessarily include  
testing of all parameters.  
1
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265  
1234567...11

中文翻译

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SN74ALVCH162260GR 替代型号

型号 品牌 替代类型 描述 数据表
SN74ALVCH162260DGGR TI

完全替代

 12-BIT TO 24-BIT MULTIPLEXED D-TYPE LATCH WITH 3-STATE OUTPUTS
74ALVCH162260GRE4 TI

类似代替

 12-Bit To 24-Bit Multiplexed D-Type Latch With 3-State Outputs 56-TSSOP -40 to 85

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