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SN74ALVCH162268_08

更新时间： 2024-11-18 05:24:51
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12-BIT TO 24-BIT REGISTERED BUS EXCHANGER WITH 3-STATE OUTPUTS

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SN74ALVCH162268_08 数据手册

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SN74ALVCH162268  
12-BIT TO 24-BIT REGISTERED BUS EXCHANGER  
WITH 3-STATE OUTPUTS  
www.ti.com  
SCES018L–AUGUST 1995–REVISED SEPTEMBER 2004  
FEATURES  
DGG OR DL PACKAGE  
(TOP VIEW)  
•
Member of the Texas Instruments Widebus™  
Family  
1
56  
55  
54  
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48  
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41  
40  
39  
38  
37  
36  
35  
34  
33  
32  
31  
30  
29  
OEA  
CLKEN1B  
2B3  
OEB  
CLKENA2  
2B4  
GND  
2B5  
2B6  
•
•
•
•
Operates From 1.65 V to 3.6 V  
Max tpd of 4.8 ns at 3.3 V  
2
3
±24-mA Output Drive at 3.3 V  
4
GND  
2B2  
2B1  
B-Port Outputs Have Equivalent 26-Ω Series  
Resistors, So No External Resistors Are  
Required  
5
6
7
V
CC  
V
CC  
•
•
•
Bus Hold on Data Inputs Eliminates the Need  
for External Pullup/Pulldown Resistors  
8
A1  
A2  
A3  
GND  
A4  
A5  
2B7  
2B8  
2B9  
9
10  
11  
12  
13  
14  
15  
16  
17  
18  
19  
20  
21  
22  
23  
24  
25  
26  
27  
28  
Latch-Up Performance Exceeds 250 mA Per  
JESD 17  
GND  
2B10  
2B11  
2B12  
1B12  
1B11  
1B10  
GND  
1B9  
ESD Protection Exceeds JESD 22  
– 2000-V Human-Body Model (A114-A)  
– 200-V Machine Model (A115-A)  
A6  
A7  
A8  
A9  
GND  
A10  
A11  
A12  
DESCRIPTION/ORDERING INFORMATION  
This 12-bit to 24-bit registered bus exchanger is  
designed for 1.65-V to 3.6-V VCC operation.  
1B8  
1B7  
The SN74ALVCH162268 is used for applications in  
which data must be transferred from a narrow  
high-speed bus to a wide, lower-frequency bus.  
V
CC  
V
CC  
1B1  
1B2  
1B6  
1B5  
The device provides synchronous data exchange  
between the two ports. Data is stored in the internal  
registers on the low-to-high transition of the clock  
(CLK) input when the appropriate clock-enable  
(CLKEN) inputs are low. The select (SEL) line is  
synchronous with CLK and selects 1B or 2B input  
data for the A outputs.  
GND  
1B3  
CLKEN2B  
SEL  
GND  
1B4  
CLKENA1  
CLK  
For data transfer in the A-to-B direction, a two-stage pipeline is provided in the A-to-1B path, with a single  
storage register in the A-to-2B path. Proper control of these inputs allows two sequential 12-bit words to be  
presented synchronously as a 24-bit word on the B port. Data flow is controlled by the active-low output enables  
(OEA, OEB). These control terminals are registered, so bus direction changes are synchronous with CLK.  
The B outputs, which are designed to sink up to 12 mA, include equivalent 26-Ω resistors to reduce overshoot  
and undershoot.  
ORDERING INFORMATION  
TA  
PACKAGE(1)  
ORDERABLE PART NUMBER  
SN74ALVCH162268DL  
SN74ALVCH162268DLR  
SN74ALVCH162268GR  
SN74ALVCH162268KR  
74ALVCH162268ZQLR  
TOP-SIDE MARKING  
ALVCH162268  
ALVCH162268  
VH2268  
Tube  
SSOP - DL  
Tape and reel  
Tape and reel  
-40°C to 85°C  
TSSOP - DGG  
VFBGA - GQL  
Tape and reel  
VFBGA - ZQL (Pb-free)  
(1) Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are available at  
www.ti.com/sc/package.  
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas  
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.  
Widebus is a trademark of Texas Instruments.  
PRODUCTION DATA information is current as of publication date.  
Copyright © 1995–2004, Texas Instruments Incorporated  
Products conform to specifications per the terms of the Texas  
Instruments standard warranty. Production processing does not  
necessarily include testing of all parameters.  
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