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SN74ALVCH162268

更新时间： 2024-11-17 23:09:43
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德州仪器 - TI 输出元件
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11页 154K
描述
12-BIT TO 24-BIT REGISTERED BUS EXCHANGER WITH 3-STATE OUTPUTS

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SN74ALVCH162268 数据手册

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SN74ALVCH162268  
12-BIT TO 24-BIT REGISTERED BUS EXCHANGER  
WITH 3-STATE OUTPUTS  
SCES018G – AUGUST 1995 – REVISED JUNE 1999  
DGG OR DL PACKAGE  
(TOP VIEW)  
Member of the Texas Instruments  
Widebus Family  
EPIC (Enhanced-Performance Implanted  
CMOS) Submicron Process  
OEA  
CLKEN1B  
2B3  
OEB  
CLKENA2  
2B4  
GND  
2B5  
2B6  
1
56  
55  
54  
53  
52  
51  
50  
49  
48  
47  
46  
45  
44  
43  
42  
41  
40  
39  
38  
37  
36  
35  
34  
33  
32  
31  
30  
29  
2
B-Port Outputs Have Equivalent 26-Ω  
Series Resistors, So No External Resistors  
Are Required  
3
GND  
2B2  
2B1  
4
5
ESD Protection Exceeds 2000 V Per  
MIL-STD-883, Method 3015; Exceeds 200 V  
Using Machine Model (C = 200 pF, R = 0)  
6
V
V
7
CC  
CC  
A1  
A2  
A3  
GND  
A4  
A5  
A6  
A7  
A8  
2B7  
2B8  
2B9  
8
9
Latch-Up Performance Exceeds 250 mA Per  
JESD 17  
10  
11  
12  
13  
14  
15  
16  
17  
18  
19  
20  
21  
22  
23  
24  
25  
26  
27  
28  
GND  
2B10  
2B11  
2B12  
1B12  
1B11  
1B10  
GND  
1B9  
Bus Hold on Data Inputs Eliminates the  
Need for External Pullup/Pulldown  
Resistors  
Package Options Include Plastic Shrink  
Small-Outline (DL) and Thin Shrink  
Small-Outline (DGG) Packages  
NOTE: For tape and reel order entry:  
A9  
GND  
A10  
A11  
A12  
The DGGR package is abbreviated to GR.  
description  
1B8  
1B7  
This 12-bit to 24-bit registered bus exchanger is  
V
V
CC  
CC  
designed for 1.65-V to 3.6-V V  
operation.  
CC  
1B1  
1B2  
GND  
1B6  
1B5  
GND  
1B4  
CLKENA1  
CLK  
The SN74ALVCH162268 is used for applications  
in which data must be transferred from a narrow  
high-speed bus to a wide, lower-frequency bus.  
1B3  
CLKEN2B  
SEL  
The device provides synchronous data exchange  
between the two ports. Data is stored in the  
internal registers on the low-to-high transition of  
the clock (CLK) input when the appropriate  
clock-enable (CLKEN) inputs are low. The select  
(SEL) line is synchronous with CLK and selects  
1B or 2B input data for the A outputs.  
For data transfer in the A-to-B direction, a two-stage pipeline is provided in the A-to-1B path, with a single  
storage register in the A-to-2B path. Proper control of these inputs allows two sequential 12-bit words to be  
presented synchronously as a 24-bit word on the B port. Data flow is controlled by the active-low output enables  
(OEA, OEB). These control terminals are registered, so bus direction changes are synchronous with CLK.  
The B outputs, which are designed to sink up to 12 mA, include equivalent 26-Ω resistors to reduce overshoot  
and undershoot.  
To ensure the high-impedance state during power up or power down, a clock pulse should be applied as soon  
as possible and OE should be tied to V  
through a pullup resistor; the minimum value of the resistor is  
CC  
determined by the current-sinking capability of the driver. Due to OE being routed through a register, the active  
state of the outputs cannot be determined prior to the arrival of the first clock pulse.  
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of  
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.  
EPIC and Widebus are trademarks of Texas Instruments Incorporated.  
Copyright 1999, Texas Instruments Incorporated  
PRODUCTION DATA information is current as of publication date.  
Products conform to specifications per the terms of Texas Instruments  
standard warranty. Production processing does not necessarily include  
testing of all parameters.  
1
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265  
1234567...11

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