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74ALVCH162373GRG4 PDF预览

74ALVCH162373GRG4

更新时间： 2024-11-18 12:54:15
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德州仪器 - TI 锁存器输出元件
页数 文件大小 规格书
15页 809K
描述
16-BIT TRANSPARENT D-TYPE LATCH WITH 3-STATE OUTPUTS

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74ALVCH162373GRG4 技术参数

是否Rohs认证： 符合生命周期：Obsolete
零件包装代码：TSSOP包装说明：TSSOP, TSSOP48,.3,20
针数：48Reach Compliance Code：compliant
HTS代码：8542.39.00.01风险等级：5.14
系列：ALVC/VCX/AJESD-30 代码：R-PDSO-G48
JESD-609代码：e4长度：12.5 mm
负载电容（CL）：50 pF逻辑集成电路类型：BUS DRIVER
最大I（ol）：0.012 A湿度敏感等级：1
位数：8功能数量：2
端口数量：2端子数量：48
最高工作温度：85 °C最低工作温度：-40 °C
输出特性：3-STATE WITH SERIES RESISTOR输出极性：TRUE
封装主体材料：PLASTIC/EPOXY封装代码：TSSOP
封装等效代码：TSSOP48,.3,20封装形状：RECTANGULAR
封装形式：SMALL OUTLINE, THIN PROFILE, SHRINK PITCH包装方法：TAPE AND REEL
峰值回流温度（摄氏度）：260电源：3.3 V
Prop。Delay @ Nom-Sup：4 ns传播延迟（tpd）：6.6 ns
认证状态：Not Qualified座面最大高度：1.2 mm
子类别：FF/Latches最大供电电压 (Vsup)：3.6 V
最小供电电压 (Vsup)：1.65 V标称供电电压 (Vsup)：1.8 V
表面贴装：YES技术：CMOS
温度等级：INDUSTRIAL端子面层：Nickel/Palladium/Gold (Ni/Pd/Au)
端子形式：GULL WING端子节距：0.5 mm
端子位置：DUAL处于峰值回流温度下的最长时间：NOT SPECIFIED
宽度：6.1 mmBase Number Matches：1

74ALVCH162373GRG4 数据手册

 浏览型号74ALVCH162373GRG4的Datasheet PDF文件第2页浏览型号74ALVCH162373GRG4的Datasheet PDF文件第3页浏览型号74ALVCH162373GRG4的Datasheet PDF文件第4页浏览型号74ALVCH162373GRG4的Datasheet PDF文件第5页浏览型号74ALVCH162373GRG4的Datasheet PDF文件第6页浏览型号74ALVCH162373GRG4的Datasheet PDF文件第7页 
SN74ALVCH162373  
16-BIT TRANSPARENT D-TYPE LATCH  
WITH 3-STATE OUTPUTS  
www.ti.com  
SCES583A–JULY 2004–REVISED OCTOBER 2004  
FEATURES  
DGG OR DL PACKAGE  
(TOP VIEW)  
•
•
•
Member of the Texas Instruments Widebus™  
Family  
48  
47  
46  
45  
44  
43  
42  
41  
40  
39  
38  
37  
36  
35  
34  
33  
32  
31  
30  
29  
28  
27  
26  
25  
1
1OE  
1Q1  
1Q2  
GND  
1Q3  
1Q4  
1LE  
1D1  
1D2  
GND  
1D3  
1D4  
Bus Hold on Data Inputs Eliminates the Need  
for External Pullup/Pulldown Resistors  
2
3
Output Ports Have Equivalent 26-Ω Series  
Resistors, So No External Resistors Are  
Required  
4
5
6
•
•
Latch-Up Performance Exceeds 250 mA Per  
JESD 17  
7
V
CC  
V
CC  
8
1Q5  
1Q6  
GND  
1Q7  
1Q8  
2Q1  
2Q2  
GND  
2Q3  
2Q4  
1D5  
1D6  
GND  
1D7  
1D8  
2D1  
2D2  
GND  
2D3  
2D4  
ESD Protection Exceeds JESD 22  
– 2000-V Human-Body Model (A114-A)  
– 200-V Machine Model (A115-A)  
9
10  
11  
12  
13  
14  
15  
16  
17  
18  
19  
20  
21  
22  
23  
24  
DESCRIPTION/ORDERING INFORMATION  
This 16-bit transparent D-type latch is designed for  
1.65-V to 3.6-V VCC operation.  
The SN74ALVCH162373 is particularly suitable for  
implementing buffer registers, I/O ports, bidirectional  
bus drivers, and working registers. This device can  
be used as two 8-bit latches or one 16-bit latch.  
When the latch-enable (LE) input is high, the Q  
outputs follow the data (D) inputs. When LE is taken  
low, the Q outputs are latched at the levels set up at  
the D inputs.  
V
CC  
V
CC  
2Q5  
2Q6  
GND  
2Q7  
2Q8  
2OE  
2D5  
2D6  
GND  
2D7  
2D8  
2LE  
A buffered output-enable (OE) input can be used to  
place the eight outputs in either a normal logic state  
(high or low logic levels) or the high-impedance state.  
In the high-impedance state, the outputs neither load  
nor drive the bus lines significantly. The  
high-impedance state and the increased drive provide  
the capability to drive bus lines without need for  
interface or pullup components. OE does not affect  
internal operations of the latch. Old data can be  
retained or new data can be entered while the  
outputs are in the high-impedance state.  
The outputs, which are designed to sink up to 12 mA, include equivalent 26-Ω resistors to reduce overshoot and  
undershoot.  
ORDERING INFORMATION  
TA  
PACKAGE(1)  
ORDERABLE PART NUMBER  
SN74ALVCH162373DL  
SN74ALVCH162373LR  
SN74ALVCH162373GR  
SN74ALVCH162373KR  
TOP-SIDE MARKING  
Tube  
SSOP - DL  
ALVCH162373  
Tape and reel  
Tape and reel  
Tape and reel  
-40°C to 85°C  
TSSOP - DGG  
VFBGA - GQL  
ALVCH162373  
VH2373  
(1) Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are available at  
www.ti.com/sc/package.  
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas  
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.  
Widebus is a trademark of Texas Instruments.  
PRODUCTION DATA information is current as of publication date.  
Copyright © 2004, Texas Instruments Incorporated  
Products conform to specifications per the terms of the Texas  
Instruments standard warranty. Production processing does not  
necessarily include testing of all parameters.  
1234567...15

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74ALVCH162373GRG4 替代型号

型号 品牌 替代类型 描述 数据表
SN74ALVCH162373GR TI

完全替代

 16-BIT TRANSPARENT D-TYPE LATCH WITH 3-STATE OUTPUTS

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