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Datasheet > 74AHC259PW,112
74AHC259PW,112 PDF预览

74AHC259PW,112

更新时间： 2024-01-30 02:21:33
品牌 Logo 应用领域
恩智浦 - NXP 光电二极管输出元件逻辑集成电路触发器
页数 文件大小 规格书
17页 100K
描述
IC AHC SERIES, OCTAL LOW LEVEL TRIGGERED D LATCH, TRUE OUTPUT, PDSO16, 4.40 MM, PLASTIC, SOT-403-1, TSSOP-16, FF/Latch

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74AHC259PW,112 技术参数

是否无铅： 不含铅是否Rohs认证： 符合
生命周期：Obsolete零件包装代码：TSSOP
包装说明：4.40 MM, PLASTIC, SOT-403-1, TSSOP-16针数：16
Reach Compliance Code：compliantHTS代码：8542.39.00.01
风险等级：5.83系列：AHC
JESD-30 代码：R-PDSO-G16JESD-609代码：e4
长度：5 mm负载电容（CL）：50 pF
逻辑集成电路类型：D LATCH最大I（ol）：0.008 A
湿度敏感等级：1位数：1
功能数量：8端子数量：16
最高工作温度：125 °C最低工作温度：-40 °C
输出极性：TRUE封装主体材料：PLASTIC/EPOXY
封装代码：TSSOP封装等效代码：TSSOP16,.25
封装形状：RECTANGULAR封装形式：SMALL OUTLINE, THIN PROFILE, SHRINK PITCH
包装方法：TUBE峰值回流温度（摄氏度）：260
电源：2/5.5 VProp。Delay @ Nom-Sup：12 ns
传播延迟（tpd）：18.5 ns认证状态：Not Qualified
座面最大高度：1.1 mm子类别：FF/Latches
最大供电电压 (Vsup)：5.5 V最小供电电压 (Vsup)：2 V
标称供电电压 (Vsup)：5 V表面贴装：YES
技术：CMOS温度等级：AUTOMOTIVE
端子面层：Nickel/Palladium/Gold (Ni/Pd/Au)端子形式：GULL WING
端子节距：0.65 mm端子位置：DUAL
处于峰值回流温度下的最长时间：30触发器类型：LOW LEVEL
宽度：4.4 mmBase Number Matches：1

74AHC259PW,112 数据手册

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74AHC259; 74AHCT259  
8-bit addressable latch  
Rev. 02 — 15 May 2008  
Product data sheet  
1. General description  
The 74AHC259; 74AHCT259 is a high-speed Si-gate CMOS device and is pin compatible  
with Low-power Schottky TTL (LSTTL). It is specified in compliance with JEDEC standard  
No. 7-A.  
The 74AHC259; 74AHCT259 is a high-speed 8-bit addressable latch designed for general  
purpose storage applications in digital systems. It is a multifunctional device capable of  
storing single-line data in eight addressable latches and providing a 3-to-8 decoder and  
multiplexer function with active HIGH outputs (Q0 to Q7). It also incorporates an active  
LOW common reset (MR) for resetting all latches as well as an active LOW enable input  
(LE).  
The 74AHC259; 74AHCT259 has four modes of operation:  
• In the addressable latch mode, data on the data line (D) is written into the addressed  
latch. The addressed latch will follow the data input with all non-addressed latches  
remaining in their previous states.  
• In the memory mode, all latches remain in their previous states and are unaffected by  
the data or address inputs.  
• In the 3-to-8 decoding or demultiplexing mode, the addressed output follows the state  
of the data input (D) with all other outputs in the LOW state.  
• In the reset mode, all outputs are LOW and unaffected by the address inputs  
(A0 to A2) and data input (D).  
When operating the 74AHC259; 74AHCT259 as an address latch, changing more than  
one bit of the address could impose a transient-wrong address. Therefore, this should  
only be done while in the memory mode.  
2. Features  
I Balanced propagation delays  
I All inputs have Schmitt-trigger actions  
I Combines demultiplexer and 8-bit latch  
I Serial-to-parallel capability  
I Output from each storage bit available  
I Random (addressable) data entry  
I Easily expandable  
I Common reset input  
I Useful as a 3-to-8 active HIGH decoder  
I Inputs accept voltages higher than VCC  
 
 
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74AHC259PW,112 替代型号

型号 品牌 替代类型 描述 数据表
74AHC259D NXP

类似代替

 8-bit addressable latch

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