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74AHC259PW-Q100 PDF预览

74AHC259PW-Q100

更新时间： 2024-09-26 14:47:39
品牌 Logo 应用领域
恩智浦 - NXP 光电二极管逻辑集成电路触发器
页数 文件大小 规格书
19页 138K
描述
IC D LATCH, FF/Latch

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中文翻译

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74AHC259PW-Q100 技术参数

生命周期：Obsolete零件包装代码：TSSOP
包装说明：TSSOP,针数：16
Reach Compliance Code：unknownHTS代码：8542.39.00.01
风险等级：5.83系列：AHC/VHC/H/U/V
JESD-30 代码：R-PDSO-G16长度：5 mm
逻辑集成电路类型：D LATCH位数：1
功能数量：1端子数量：16
最高工作温度：125 °C最低工作温度：-40 °C
输出极性：TRUE封装主体材料：PLASTIC/EPOXY
封装代码：TSSOP封装形状：RECTANGULAR
封装形式：SMALL OUTLINE, THIN PROFILE, SHRINK PITCH传播延迟（tpd）：19 ns
筛选级别：AEC-Q100座面最大高度：1.1 mm
最大供电电压 (Vsup)：5.5 V最小供电电压 (Vsup)：2 V
标称供电电压 (Vsup)：5 V表面贴装：YES
技术：CMOS温度等级：AUTOMOTIVE
端子形式：GULL WING端子节距：0.65 mm
端子位置：DUAL触发器类型：LOW LEVEL
宽度：4.4 mmBase Number Matches：1

74AHC259PW-Q100 数据手册

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74AHC259-Q100;  
74AHCT259-Q100  
8-bit addressable latch  
Rev. 1 — 22 July 2013  
Product data sheet  
1. General description  
The 74AHC259-Q100; 74AHCT259-Q100 is a high-speed Si-gate CMOS device and is  
pin compatible with Low-power Schottky TTL (LSTTL). It is specified in compliance with  
JEDEC standard No. 7-A.  
The 74AHC259-Q100; 74AHCT259-Q100 is a high-speed 8-bit addressable latch  
designed for general purpose storage applications in digital systems. It is a multifunctional  
device capable of storing single-line data in eight addressable latches. It provides a 3-to-8  
decoder and multiplexer function with active HIGH outputs (Q0 to Q7). It also incorporates  
an active LOW common reset (MR) for resetting all latches as well as an active LOW  
enable input (LE).  
The 74AHC259-Q100; 74AHCT259-Q100 has four modes of operation:  
• In the addressable latch mode, data on the data line (D) is written into the addressed  
latch. The addressed latch follows the data input with all non-addressed latches  
remaining in their previous states.  
• In the memory mode, all latches remain in their previous states and are unaffected by  
the data or address inputs.  
• In the 3-to-8 decoding or demultiplexing mode, the addressed output follows the state  
of the data input (D) with all other outputs in the LOW state.  
• In the reset mode, all outputs are LOW and unaffected by the address inputs  
(A0 to A2) and data input (D).  
When operating the 74AHC259-Q100; 74AHCT259-Q100 as an address latch, changing  
more than 1 bit of the address could impose a transient-wrong address. Therefore, only  
change more than 1 bit while in the memory mode.  
This product has been qualified to the Automotive Electronics Council (AEC) standard  
Q100 (Grade 1) and is suitable for use in automotive applications.  
2. Features and benefits  
Automotive product qualification in accordance with AEC-Q100 (Grade 1)  
Specified from 40 C to +85 C and from 40 C to +125 C  
Balanced propagation delays  
All inputs have Schmitt-trigger actions  
Combines demultiplexer and 8-bit latch  
Serial-to-parallel capability  
 
 
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