Datasheet > 74AHC273_08

74AHC273_08

更新时间： 2024-09-26 12:50:03

品牌	Logo	应用领域
恩智浦 - NXP		触发器
页数	文件大小	规格书
18页	111K
描述
Octal D-type flip-flop with reset; positive-edge trigger

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数据手册

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74AHC273_08 数据手册

74AHC273; 74AHCT273

Octal D-type ﬂip-ﬂop with reset; positive-edge trigger

Rev. 03 — 13 May 2008

Product data sheet

1. General description

The 74AHC273; 74AHCT273 is a high-speed Si-gate CMOS device and is pin compatible

with Low-power Schottky TTL (LSTTL). It is speciﬁed in compliance with JEDEC standard

No. 7-A.

The 74AHC273; 74AHCT273 has eight edge-triggered, D-type ﬂip-ﬂops with individual D

inputs and Q outputs.

The common clock (CP) and master reset (MR) inputs, load and reset (clear) all ﬂip-ﬂops

simultaneously.

The state of each D input, one set-up time before the LOW-to-HIGH clock transition, is

transferred to the corresponding output (Qn) of the ﬂip-ﬂop.

All outputs will be forced LOW, independent of clock or data inputs, by a LOW on the MR

input.

The device is useful for applications where only the true output is required and the clock

and master reset are common to all storage elements.

2. Features

I Balanced propagation delays

I All inputs have Schmitt-trigger actions

I Inputs accept voltages higher than V_CC

I Ideal buffer for MOS microcontroller or memory

I Common clock and master reset

I Related product versions:

N 74AHC377; 74AHCT377 for clock enable version

N 74AHC373; 74AHCT373 for transparent latch version

N 74AHC374; 74AHCT374 for 3-state version

I Input levels:

N For 74AHC273: CMOS level

N For 74AHCT273: TTL level

I ESD protection:

N HBM EIA/JESD22-A114E exceeds 2000 V

N MM EIA/JESD22-A115-A exceeds 200 V

N CDM EIA/JESD22-C101C exceeds 1000 V

I Multiple package options

I Speciﬁed from −40 °C to +85 °C and from −40 °C to +125 °C

12 3 4 5 6 7...18

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