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74AHC164D,118 PDF预览

74AHC164D,118

更新时间: 2024-09-14 14:40:15
品牌 Logo 应用领域
恩智浦 - NXP /
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18页 92K
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74AHC164D,118 数据手册

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74AHC164; 74AHCT164  
8-bit serial-in/parallel-out shift register  
Rev. 03 — 24 April 2008  
Product data sheet  
1. General description  
The 74AHC164; 74AHCT164 shift register is a high-speed Si-gate CMOS device and is  
pin compatible with Low-power Schottky TTL (LSTTL). It is specified in compliance with  
JEDEC standard No. 7A.  
The 74AHC164; 74AHCT164 input signals are 8-bit serial through one of two inputs (DSA  
or DSB); either input can be used as an active HIGH enable for data entry through the  
other input. Both inputs must be connected together or an unused input must be tied  
HIGH.  
Data shifts one place to the right on each LOW-to-HIGH transition of the clock input (CP)  
and enters into output Q0, which is a logical AND of the two data inputs (DSA and DSB)  
that existed one set-up time prior to the rising clock edge.  
A LOW-level on the master reset (MR) input overrides all other inputs and clears the  
register asynchronously, forcing all outputs LOW.  
2. Features  
I Balanced propagation delays  
I All inputs have Schmitt-trigger actions  
I Inputs accept voltages higher than VCC  
I Input levels:  
N For 74AHC164: CMOS level  
N For 74AHCT164: TTL level  
I ESD protection:  
N HBM EIA/JESD22-A114E exceeds 2000 V  
N MM EIA/JESD22-A115-A exceeds 200 V  
N CDM EIA/JESD22-C101C exceeds 1000 V  
I Multiple package options  
I Specified from 40 °C to +85 °C and from 40 °C to +125 °C  
 
 

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