Datasheet > 74AHC164-Q100

74AHC164-Q100

更新时间： 2024-09-15 00:57:47

品牌	Logo	应用领域
安世 - NEXPERIA		/
页数	文件大小	规格书
19页	726K
描述
Automotive product qualification in accordance with AEC-Q100

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74AHC164-Q100 数据手册

74AHC164-Q100;

74AHCT164-Q100

8-bit serial-in/parallel-out shift register

Rev. 1 — 5 July 2013

Product data sheet

1. General description

The 74AHC164-Q100; 74AHCT164-Q100 shift register is a high-speed Si-gate CMOS

device and is pin compatible with Low-power Schottky TTL (LSTTL). It is specified in

compliance with JEDEC standard No. 7A.

The 74AHC164-Q100; 74AHCT164-Q100 input signals are 8-bit serial through one of two

inputs (DSA or DSB). Either input can be used as an active HIGH enable for data entry

through the other input. Both inputs must be connected together or an unused input must

be tied HIGH.

Data shifts one place to the right on each LOW-to-HIGH transition of the clock input (CP).

It enters into output Q0, which is a logical AND of the two data inputs (DSA and DSB).

These data inputs existed one set-up time, prior to the rising clock edge.

A LOW-level on the master reset (MR) input overrides all other inputs and clears the

This product has been qualified to the Automotive Electronics Council (AEC) standard

Q100 (Grade 1) and is suitable for use in automotive applications.

2. Features and benefits

 Automotive product qualification in accordance with AEC-Q100 (Grade 1)

 Specified from 40 C to +85 C and from 40 C to +125 C

 Balanced propagation delays

 All inputs have Schmitt-trigger actions

 Inputs accept voltages higher than V_CC

 Input levels:

 For 74AHC164-Q100: CMOS level

 For 74AHCT164-Q100: TTL level

 ESD protection:

 MIL-STD-883, method 3015 exceeds 2000 V

 HBM JESD22-A114F exceeds 2000 V

 MM JESD22-A115-A exceeds 200 V (C = 200 pF, R = 0 )

 Multiple package options

12 3 4 5 6 7...19

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