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72V3633L20PF9 PDF预览

72V3633L20PF9

更新时间: 2024-11-24 09:58:35
品牌 Logo 应用领域
艾迪悌 - IDT /
页数 文件大小 规格书
28页 314K
描述
TQFP-128, Tray

72V3633L20PF9 数据手册

 浏览型号72V3633L20PF9的Datasheet PDF文件第2页浏览型号72V3633L20PF9的Datasheet PDF文件第3页浏览型号72V3633L20PF9的Datasheet PDF文件第4页浏览型号72V3633L20PF9的Datasheet PDF文件第5页浏览型号72V3633L20PF9的Datasheet PDF文件第6页浏览型号72V3633L20PF9的Datasheet PDF文件第7页 
3.3 VOLT CMOS SyncFIFOTM WITH  
BUS-MATCHING  
256 x 36 , 512 x 36  
1,024 x 36  
IDT72V3623  
IDT72V3633  
IDT72V3643  
Big- or Little-Endian format for word and byte bus sizes  
FEATURES:  
Reset clears data and configures FIFO, Partial Reset clears data  
but retains configuration settings  
Mailbox bypass registers for each FIFO  
Free-running CLKA and CLKB may be asynchronous or  
coincident (simultaneous reading and writing of data on a single  
clock edge is permitted)  
Memory storage capacity:  
IDT72V3623–256 x 36  
IDT72V3633–512 x 36  
IDT72V3643–1,024 x 36  
Clock frequencies up to 100 MHz (6.5 ns access time)  
Clocked FIFO buffering data from Port A to Port B  
IDT Standard timing (using EF and FF) or First Word Fall  
Through Timing (using OR and IR flag functions)  
Programmable Almost-Empty and Almost-Full flags; each has  
three default offsets (8, 16 and 64)  
Serial or parallel programming of partial flags  
Port B bus sizing of 36 bits (long word), 18 bits (word) and 9 bits  
(byte)  
Easily expandable in width and depth  
Auto power down minimizes power dissipation  
Available in a space-saving 128-pin Thin Quad Flatpack (TQFP)  
Pin and functionally compatible versions of the 5V operating  
IDT723623/723633/723643  
Industrial temperature range (–40°C to +85°C) is available  
FUNCTIONAL BLOCK DIAGRAM  
MBF1  
Mail 1  
Register  
CLKA  
CSA  
Port-A  
W/RA  
Control  
ENA  
Logic  
MBA  
36  
RAM ARRAY  
36  
36  
FIFO1  
Mail1,  
Mail2,  
Reset  
Logic  
256 x 36  
512 x 36  
RS1  
RS2  
PRS  
1,024 x 36  
36  
Write  
Pointer  
Read  
Pointer  
A0-A35  
B0-B35  
Status Flag  
Logic  
EF/OR  
AE  
FF/IR  
AF  
36  
36  
SPM  
FS0/SD  
FS1/SEN  
Programmable Flag  
Offset Registers  
Timing  
Mode  
FWFT  
10  
CLKB  
CSB  
W/RB  
ENB  
MBB  
BE  
Port-B  
Control  
Logic  
BM  
SIZE  
Mail 2  
Register  
4662 drw01  
MBF2  
IDTandtheIDTlogoaretrademarkofIntegratedDeviceTechnology,Inc. SyncFIFOisatrademarkofIntegratedDeviceTechnology,Inc.  
AUGUST 2001  
COMMERCIAL TEMPERATURE RANGE  
1
2001 Integrated Device Technology, Inc. All rights reserved. Product specifications subject to change without notice.  
DSC-4662/4  

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