Datasheet > 72V3641

72V3641

更新时间： 2024-11-24 14:57:23

品牌	Logo	应用领域
瑞萨 - RENESAS		先进先出芯片
页数	文件大小	规格书
21页	445K
描述
1K x 36 SyncFIFO, 3.3V

阅读下载

中文翻译

获取价格

数据手册

如果您发现信息不准确，欢迎纠错

72V3641 数据手册

3.3 VOLT CMOS SyncFIFO^TM

512 x 36

1,024 x 36

72V3631

72V3641

• Available in space-saving 120-pin thin quad flat package (TQFP)

• Pin and functionally compatible versions of the 5V operating

723631/723641

• Easily expandable in width and depth

• Green parts are available, see ordering information

FEATURES

• Storage capacity:

72V3631 - 512 x 36

72V3641 - 1,024 x 36

• Supports clock frequencies up to 67 MHz

• Fast access times of 10ns

DESCRIPTION

• Free-running CLKA and CLKB can be asynchronous or coinci-

dent (permits simultaneous reading and writing of data on a

single clock edge)

• Clocked FIFO buffering data from Port A to Port B

• Synchronous read retransmit capability

• Mailbox register in each direction

• Programmable Almost-Full and Almost-Empty flags

• Microprocessor interface control logic

• Input Ready (IR) and Almost-Full (AF) flags synchronized by

CLKA

• Output Ready (OR) and Almost-Empty (AE) flags synchronized

by CLKB

The72V3631/72V3641arepinandfunctionallycompatibleversonsofthe

723631/723641,designedtorunoffa3.3Vsupplyforexceptionallylow-power

consumption. Thesedevicesaremonolithichigh-speed,low-power,CMOS

clockedFIFOmemory. Itsupportsclockfrequenciesupto67MHzandhasread

accesstimesasfastas10ns. The512/1,024x36dual-portSRAMFIFObuffers

datafromportAtoPortB. TheFIFOmemoryhasretransmitcapability,which

allowspreviouslyreaddatatobeaccessedagain. TheFIFOoperatesinFirst

WordFallThroughmodeandhasflagstoindicateemptyandfullconditionsand

conditions and two programmable flags (Almost-Full and Almost-Empty) to

indicatewhenaselectednumberofwordsisstoredinmemory. Communication

FUNCTIONAL BLOCK DIAGRAM

MBF1

Mail 1

CLKA

CSA

W/RA

ENA

MBA

Port-A

Control

Logic

RAM ARRAY

512 x 36

1,024 x 36

Reset

Logic

RST

RTM

Read

Pointer

Write

Pointer

RFM

A0 - A35

B0 - B35

Status Flag

Logic

Flag Offset

Registers

FS⁰/SD

FS1/SE

CLKB

CSB

W/RB

ENB

MBB

Port-B

Control

Logic

Mail 2

4658 drw 01

MBF2

COMMERCIAL TEMPERATURE RANGE

Oct.29.21

12 3 4 5 6 7...21

中文翻译

下载PDF

与72V3641相关器件

型号	品牌	获取价格	描述	数据表
72V3641L15PFG	IDT	获取价格	3.3 VOLT CMOS SyncFIFO
72V3641L15PFG8	IDT	获取价格	3.3 VOLT CMOS SyncFIFO
72V3641L20PF	IDT	获取价格	TQFP-120, Tray
72V3641L20PFG	IDT	获取价格	FIFO, 1KX36, 12ns, Synchronous, CMOS, PQFP120, GREEN, TQFP-120
72V3641L20PQFG	IDT	获取价格	FIFO, 1KX36, 12ns, Synchronous, CMOS, PQFP132, GREEN, PLASTIC, QFP-132
72V3642	RENESAS	获取价格	1K x 36 x 2 SyncBiFIFO, 3.3V
72V3642L10PF	IDT	获取价格	TQFP-120, Tray
72V3642L10PFG	IDT	获取价格	3.3 VOLT CMOS SyncBiFIFO
72V3642L10PFG8	IDT	获取价格	3.3 VOLT CMOS SyncBiFIFO
72V3642L10PQF	IDT	获取价格	PQFP-132, Tray