Datasheet > 72V3640L15PFI9

72V3640L15PFI9

更新时间： 2024-11-24 08:43:15

品牌	Logo	应用领域
艾迪悌 - IDT		先进先出芯片
页数	文件大小	规格书
46页	460K
描述
FIFO, 1KX36, 10ns, Synchronous, CMOS, PQFP128, PLASTIC, TQFP-128

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中文翻译

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数据手册

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72V3640L15PFI9 数据手册

3.3V HIGH-DENSITY SUPERSYNC™ II 36-BIT FIFO

1,024 x 36, 2,048 x 36

4,096 x 36, 8,192 x 36

16,384 x 36, 32,768 x 36

IDT72V3640,IDT72V3650

IDT72V3660,IDT72V3670

IDT72V3680, IDT72V3690

• Zero latency retransmit

FEATURES:

• Auto power down minimizes standby power consumption

• Master Reset clears entire FIFO

• Partial Reset clears data, but retains programmable settings

• Empty, Full and Half-Full flags signal FIFO status

• Programmable Almost-Empty and Almost-Full flags, each flag can

default to one of eight preselected offsets

• Selectable synchronous/asynchronous timing modes for Almost-

Empty and Almost-Full flags

• Program programmable flags by either serial or parallel means

• Select IDT Standard timing (using EF and FF flags) or First Word

Fall Through timing (using OR and IR flags)

• Output enable puts data outputs into high impedance state

• Easily expandable in depth and width

• JTAG port, provided for Boundary Scan function (PBGA Only)

• Independent Read and Write Clocks (permit reading and writing

simultaneously)

• Availableina128-pinThinQuadFlatPack(TQFP)ora144-pinPlastic

Ball Grid Array (PBGA) (with additional features)

• High-performance submicron CMOS technology

• Industrial temperature range (–40°C to +85°C) is available

• Choose among the following memory organizations:Commercial

IDT72V3640

IDT72V3650

IDT72V3660

IDT72V3670

IDT72V3680

IDT72V3690



1,024 x 36

2,048 x 36

4,096 x 36

8,192 x 36

16,384 x 36

32,768 x 36

• Up to 166 MHz Operation of the Clocks

• UserselectableAsynchronous readand/orwriteports (PBGAOnly)

• User selectable input and output port bus-sizing

- x36 in to x36 out

- x36 in to x18 out

- x36 in to x9 out

- x18 in to x36 out

- x9 in to x36 out

• Pin to Pin compatible to the higher density of IDT72V36100 and

IDT72V36110

• Big-Endian/Little-Endian user selectable byte representation

• 5V input tolerant

• Fixed, low first word latency

FUNCTIONALBLOCKDIAGRAM

*Available on the PBGA package only.

D0 -Dn (x36, x18 or x9)

LD SEN

WEN

WCLK/WR

INPUT REGISTER

OFFSET REGISTER

FF/IR

PAF

EF/OR

PAE

FLAG

LOGIC

WRITE CONTROL

LOGIC

ASYW

FWFT/SI

PFM

RAM ARRAY

FSEL0

FSEL1

1,024 x 36, 2,048 x 36

4,096 x 36, 8,192 x 36

16,384 x 36, 32,768 x 36

WRITE POINTER

READ POINTER

CONTROL

LOGIC

READ

CONTROL

LOGIC

ASYR

OUTPUT REGISTER

BUS

CONFIGURATION

MRS

PRS

RESET

LOGIC

RCLK/RD

REN

TCK

TRST

JTAG CONTROL

(BOUNDARY SCAN)

TMS

TDI

TDO

4667 drw01

Q0 -Qn (x36, x18 or x9)

IDT and the IDT logo are a registered trademarks of Integrated Device Technology, Inc. The SuperSync II FIFO is a trademark of Integrated Device Technology, Inc.

COMMERCIAL AND INDUSTRIAL TEMPERATURE RANGES

JULY 2003



DSC-4667/11

12 3 4 5 6 7...46

中文翻译

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与72V3640L15PFI9相关器件

型号	品牌	获取价格	描述	数据表
72V3640L7.5PF	IDT	获取价格	FIFO, 1KX36, 5ns, Synchronous, CMOS, PQFP128, PLASTIC, TQFP-128
72V3640L7-5BBGI8	IDT	获取价格	FIFO, 1KX36, 5ns, Synchronous, CMOS, PBGA144, 13 X 13 MM, 1 MM PITCH, GREEN, PLASTIC, BGA-
72V3640L7-5PFGI	IDT	获取价格	FIFO, 1KX36, 5ns, Synchronous, CMOS, PQFP128, GREEN, PLASTIC, TQFP-128
72V3641	RENESAS	获取价格	1K x 36 SyncFIFO, 3.3V
72V3641L15PFG	IDT	获取价格	3.3 VOLT CMOS SyncFIFO
72V3641L15PFG8	IDT	获取价格	3.3 VOLT CMOS SyncFIFO
72V3641L20PF	IDT	获取价格	TQFP-120, Tray
72V3641L20PFG	IDT	获取价格	FIFO, 1KX36, 12ns, Synchronous, CMOS, PQFP120, GREEN, TQFP-120
72V3641L20PQFG	IDT	获取价格	FIFO, 1KX36, 12ns, Synchronous, CMOS, PQFP132, GREEN, PLASTIC, QFP-132
72V3642	RENESAS	获取价格	1K x 36 x 2 SyncBiFIFO, 3.3V

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