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72V3642L10PFG PDF预览

72V3642L10PFG

更新时间: 2024-11-27 00:53:23
品牌 Logo 应用领域
艾迪悌 - IDT 时钟先进先出芯片内存集成电路
页数 文件大小 规格书
29页 210K
描述
3.3 VOLT CMOS SyncBiFIFO

72V3642L10PFG 技术参数

是否无铅: 不含铅是否Rohs认证: 符合
生命周期:Active零件包装代码:TQFP
包装说明:LFQFP, QFP120,.63SQ,16针数:120
Reach Compliance Code:compliantECCN代码:EAR99
HTS代码:8542.32.00.71风险等级:5.16
Samacsys Description:TQFP 14.0 X 14.0 X 1.4 MM最长访问时间:6.5 ns
其他特性:MAIL BOX BYPASS REGISTER最大时钟频率 (fCLK):100 MHz
周期时间:10 nsJESD-30 代码:S-PQFP-G120
JESD-609代码:e3长度:14 mm
内存密度:36864 bit内存集成电路类型:BI-DIRECTIONAL FIFO
内存宽度:36湿度敏感等级:3
功能数量:1端子数量:120
字数:1024 words字数代码:1000
工作模式:SYNCHRONOUS最高工作温度:70 °C
最低工作温度:组织:1KX36
可输出:YES封装主体材料:PLASTIC/EPOXY
封装代码:LFQFP封装等效代码:QFP120,.63SQ,16
封装形状:SQUARE封装形式:FLATPACK, LOW PROFILE, FINE PITCH
并行/串行:PARALLEL峰值回流温度(摄氏度):260
电源:3.3 V认证状态:Not Qualified
座面最大高度:1.6 mm最大待机电流:0.005 A
子类别:FIFOs最大供电电压 (Vsup):3.45 V
最小供电电压 (Vsup):3.15 V标称供电电压 (Vsup):3.3 V
表面贴装:YES技术:CMOS
温度等级:COMMERCIAL端子面层:Matte Tin (Sn)
端子形式:GULL WING端子节距:0.4 mm
端子位置:QUAD处于峰值回流温度下的最长时间:30
宽度:14 mmBase Number Matches:1

72V3642L10PFG 数据手册

 浏览型号72V3642L10PFG的Datasheet PDF文件第2页浏览型号72V3642L10PFG的Datasheet PDF文件第3页浏览型号72V3642L10PFG的Datasheet PDF文件第4页浏览型号72V3642L10PFG的Datasheet PDF文件第5页浏览型号72V3642L10PFG的Datasheet PDF文件第6页浏览型号72V3642L10PFG的Datasheet PDF文件第7页 
3.3 VOLT CMOS SyncBiFIFOTM  
256 x 36 x 2  
512 x 36 x 2  
IDT72V3622  
IDT72V3632  
IDT72V3642  
1,024 x 36 x 2  
FFA/IRA, EFA/ORA, AEA, and AFA flags synchronized by CLKA  
FFB/IRB, EFB/ORB, AEB, and AFB flags synchronized by CLKB  
Select IDT Standard timing (using EFA, EFB, FFA and FFB flags  
functions) or First Word Fall Through timing (using ORA, ORB, IRA  
and IRB flag functions)  
FEATURES:  
Memory storage capacity:  
IDT72V3622  
IDT72V3632  
IDT72V3642  
256 x 36 x 2  
512 x 36 x 2  
1,024 x 36 x 2  
Available space-saving 120-pin Thin Quad Flatpack (TQFP)  
Functionally compatible to the 5V operating IDT723622/723632/  
723642  
Supports clock frequencies up to 100 MHz  
Fast access times of 6.5ns  
Free-running CLKA and CLKB may be asynchronous or coincident  
(simultaneous reading and writing of data on a single clock edge  
is permitted)  
Industrial temperature range (–40οC to +85οC) is available  
Green parts available, see ordering information  
Two independent clocked FIFOs buffering data in opposite direc-  
tions  
Mailbox bypass register for each FIFO  
Programmable Almost-Full and Almost-Empty flags  
Microprocessor Interface Control Logic  
DESCRIPTION:  
TheIDT72V3622/72V3632/72V3642arefunctionallycompatibleversions  
of the IDT723622/723632/723642, designed to run off a 3.3V supply for  
exceptionallylow-powerconsumption. Thesedevicesaremonolithic, high-  
FUNCTIONAL BLOCK DIAGRAM  
MBF1  
Mail 1  
Register  
CLKA  
CSA  
Port-A  
Control  
Logic  
W/RA  
RAM  
ENA  
ARRAY  
MBA  
256 x 36  
512 x 36  
1,024 x 36  
36  
FIFO1,  
Mail1  
Reset  
Logic  
RST1  
Write  
Pointer  
Read  
Pointer  
36  
Status Flag  
Logic  
EFB/ORB  
AEB  
FFA/IRA  
AFA  
FIFO 1  
FS  
0
1
Programmable Flag  
Offset Registers  
Timing  
Mode  
FWFT  
FS  
A
0
- A35  
10  
B0 - B35  
FIFO 2  
Status Flag  
EFA/ORA  
FFB/IRB  
AFB  
Logic  
AEA  
36  
Read  
Pointer  
Write  
Pointer  
36  
FIFO2,  
Mail2  
Reset  
Logic  
RST2  
RAM  
ARRAY  
256 x 36  
512 x 36  
CLKB  
CSB  
W/RB  
Port-B  
Control  
Logic  
1,024 x 36  
ENB  
Mail 2  
Register  
MBB  
4660 drw 01  
MBF2  
CIDTOandMtheMIDTElogRoaCrereIgAisteLredtrTadeEmaMrkoPfInEtegRrateAdDTevUiceTRecEhnologRy,IAnc NSynGcBiEFIFOisatrademarkofIntegratedDeviceTechnology,Inc.  
FEBRUARY2015  
1
©
2015 Integrated Device Technology, Inc. All rights reserved. Product specifications subject to change without notice.  
DSC-4660/9  

72V3642L10PFG 替代型号

型号 品牌 替代类型 描述 数据表
72V3642L10PF IDT

完全替代

TQFP-120, Tray
72V3642L10PFG8 IDT

完全替代

3.3 VOLT CMOS SyncBiFIFO
723642L15PFG IDT

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CMOS SyncBiFIFO

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