Datasheet > 72V3634L10PF

72V3634L10PF

更新时间： 2024-11-27 10:17:03

品牌	Logo	应用领域
艾迪悌 - IDT		/
页数	文件大小	规格书
34页	363K
描述
TQFP-128, Tray

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中文翻译

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数据手册

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72V3634L10PF 数据手册

3.3 VOLT CMOS SyncBiFIFO^TM

WITH BUS-MATCHING

256 x 36 x 2, 512 x 36 x 2,

1,024 x 36 x 2

IDT72V3624

IDT72V3634

IDT72V3644

• Port B bus sizing of 36 bits (long word), 18 bits (word) and 9 bits

(byte)

• Big- or Little-Endian format for word and byte bus sizes

• Master Reset clears data and configures FIFO, Partial Reset

clears data but retains configuration settings

• Mailbox bypass registers for each FIFO

FEATURES:

• Memory storage capacity:

IDT72V3624–256 x 36 x 2

IDT72V3634–512 x 36 x 2

IDT72V3644–1,024 x 36 x 2

• Clock frequencies up to 100 MHz (6.5ns access time)

• Two independent clocked FIFOs buffering data in opposite

directions

• Free-running CLKA and CLKB may be asynchronous or coinci-

dent (simultaneous reading and writing of data on a single clock

edge is permitted)

• Select IDT Standard timing (using EFA, EFB, FFA, and FFB

flags functions) or First Word Fall Through Timing (using ORA,

ORB, IRA, and IRB flag functions)

• Programmable Almost-Empty and Almost-Full flags; each has

three default offsets (8, 16 and 64)

• Auto power down minimizes power dissipation

• Available in space saving 128-pin Thin Quad Flatpack (TQFP)

• Pin and functionally compatible version of the 5V operating

IDT723624/723634/723644

• Industrial temperature range (–40°C to +85°C) is available

• Green parts available, see ordering information

• Serial or parallel programming of partial flags

FUNCTIONAL BLOCK DIAGRAM

MBF1

Mail 1

CLKA

Port-A

Control

Logic

CSA

W/RA

ENA

RAM ARRAY

256 x 36

MBA

512 x 36

1,024 x 36

FIFO1,

Mail1

Reset

Logic

MRS1

PRS1

Write

Pointer

Read

Pointer

Status Flag

Logic

EFB/ORB

AEB

FFA/IRA

AFA

FIFO1

FIFO2

SPM

FS0/SD

Programmable Flag

Offset Registers

Timing

Mode

FWFT

FS1/SEN

0-A35

B0-B35

EFA/ORA

Status Flag

Logic

FFB/IRB

AFB

AEA

Read

Pointer

Write

Pointer

FIFO2,

Mail2

Reset

Logic

MRS2

PRS2

RAM ARRAY

256 x 36

512 x 36

CLKB

CSB

W/RB

ENB

MBB

1,024 x 36

Port-B

Control

Logic

Mail 2

SIZE

MBF2

4664 drw01

C^IDTO^andM^theM^IDTE^logR^oaC^rereI^gA^isteL^redtrT^adeE^maM^rkoP^fInE^tegR^rateA^dDT^evU^iceTR^ecE^hnologR^y,IA^nc.N^SynG^cBE^{iFIFOisatrademarkofIntegratedDeviceTechnology,Inc.}

FEBRUARY 2009

DSC-4664/5

12 3 4 5 6 7...34

中文翻译

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与72V3634L10PF相关器件

型号	品牌	获取价格	描述	数据表
72V3634L10PF8	IDT	获取价格	TQFP-128, Reel
72V3634L10PFG	IDT	获取价格	Bi-Directional FIFO, 512X36, 6.5ns, Synchronous, CMOS, PQFP128, GREEN, TQFP-128
72V3634L12PF	IDT	获取价格	TQFP-128, Tray
72V3634L12PF8	IDT	获取价格	TQFP-128, Reel
72V3634L12PF9	IDT	获取价格	TQFP-128, Tray
72V3634L15PF	IDT	获取价格	TQFP-128, Tray
72V3634L15PF8	IDT	获取价格	TQFP-128, Reel
72V3634L15PF9	IDT	获取价格	TQFP-128, Tray
72V3636L10PF9	IDT	获取价格	TQFP-128, Tray
72V3636L10PFG	IDT	获取价格	Bi-Directional FIFO, 512X36, 6.5ns, Synchronous, CMOS, PQFP128, TQFP-128

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