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72V3614L15PF PDF预览

72V3614L15PF

更新时间: 2024-11-10 10:30:07
品牌 Logo 应用领域
艾迪悌 - IDT 时钟先进先出芯片内存集成电路
页数 文件大小 规格书
33页 345K
描述
TQFP-120, Tray

72V3614L15PF 技术参数

是否无铅: 含铅是否Rohs认证: 不符合
生命周期:Obsolete零件包装代码:TQFP
包装说明:LFQFP, QFP120,.63SQ,16针数:120
Reach Compliance Code:not_compliantECCN代码:EAR99
HTS代码:8542.32.00.71风险等级:5.67
最长访问时间:10 ns其他特性:MAIL BOX BYPASS REGISTER
最大时钟频率 (fCLK):66.7 MHz周期时间:15 ns
JESD-30 代码:S-PQFP-G120JESD-609代码:e0
长度:14 mm内存密度:2304 bit
内存集成电路类型:BI-DIRECTIONAL FIFO内存宽度:36
湿度敏感等级:4功能数量:1
端子数量:120字数:64 words
字数代码:64工作模式:SYNCHRONOUS
最高工作温度:70 °C最低工作温度:
组织:64X36可输出:YES
封装主体材料:PLASTIC/EPOXY封装代码:LFQFP
封装等效代码:QFP120,.63SQ,16封装形状:SQUARE
封装形式:FLATPACK, LOW PROFILE, FINE PITCH并行/串行:PARALLEL
峰值回流温度(摄氏度):240电源:3.3 V
认证状态:Not Qualified座面最大高度:1.6 mm
最大待机电流:0.0004 A子类别:FIFOs
最大供电电压 (Vsup):3.6 V最小供电电压 (Vsup):3 V
标称供电电压 (Vsup):3.3 V表面贴装:YES
技术:CMOS温度等级:COMMERCIAL
端子面层:Tin/Lead (Sn85Pb15)端子形式:GULL WING
端子节距:0.4 mm端子位置:QUAD
处于峰值回流温度下的最长时间:20宽度:14 mm

72V3614L15PF 数据手册

 浏览型号72V3614L15PF的Datasheet PDF文件第2页浏览型号72V3614L15PF的Datasheet PDF文件第3页浏览型号72V3614L15PF的Datasheet PDF文件第4页浏览型号72V3614L15PF的Datasheet PDF文件第5页浏览型号72V3614L15PF的Datasheet PDF文件第6页浏览型号72V3614L15PF的Datasheet PDF文件第7页 
3.3VOLTCMOSSyncBiFIFOTM WITH  
BUS-MATCHINGANDBYTESWAPPING  
64 x 36 x 2  
IDT72V3614  
Three modes of byte-order swapping on port B  
Programmable Almost-Full and Almost-Empty flags  
Microprocessor interface control logic  
FEATURES:  
Two independent clocked FIFOs (64 x 36 storage capacity each)  
buffering data in opposite directions  
EFA , FFA , AEA , and AFA flags synchronized by CLKA  
EFB , FFB , AEB , and AFB flags synchronized by CLKB  
Passive parity checking on each port  
Parity generation can be selected for each port  
Available in 132-pin plastic quad flat package (PQF), or space  
saving 120-pin thin quad flat package (TQFP)  
Pin and functionally compatible version of the 5V operating  
IDT723614  
Supports clock frequencies up to 83 MHz  
Fast access times of 8 ns  
Free-running CLKA and CLKB can be asynchronous or coinci-  
dent (simultaneous reading and writing of data on a single  
clock edge is permitted)  
Mailbox bypass Register for each FIFO  
Dynamic Port B bus sizing of 36 bits (long word), 18 bits (word),  
and 9 bits (byte)  
Selection of Big- or Little-Endian format for word and byte bus  
sizes  
Industrial temperature range (–40°C to +85°C) is available  
Green parts available, see ordering information  
FUNCTIONAL BLOCK DIAGRAM  
CLKA  
CSA  
W/RA  
ENA  
Port-A  
Control  
Logic  
MBF1  
MBA  
PEFB  
Parity  
Gen/Check  
Mail 1  
Register  
PGB  
RAM  
ARRAY  
36  
64 x 36  
RST  
Device  
Control  
ODD/  
EVEN  
Read  
Pointer  
Write  
Pointer  
EFB  
AEB  
FFA  
AFA  
Status Flag  
Logic  
FIFO1  
36  
FS0  
FS1  
Programmable Flag  
Offset Register  
B0-B35  
A0 - A35  
FIFO2  
FFB  
AFB  
EFA  
AEA  
Status Flag  
Logic  
Write  
Pointer  
Read  
Pointer  
36  
RAM  
ARRAY  
64 x 36  
PGA  
Mail 2  
Register  
Parity  
Gen/Check  
PEFA  
MBF2  
CLKB  
CSB  
W/RB  
ENB  
BE  
Port-B  
Control  
Logic  
SIZ0  
SIZ1  
SW0  
SW1  
4663 drw 01  
IDTandtheIDTlogoareregisteredtrademarksofIntegratedDeviceTechnology,Inc.SyncBiFIFOisatrademarkofIntegratedDeviceTechnology,Inc.  
COMMERCIAL TEMPERATURE RANGE  
FEBRUARY 2009  
1
©2009 Integrated Device Technology, Inc. All rights reserved. Product specifications subject to change without notice.  
DSC-4663/3  

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