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72V3622L10PQFG PDF预览

72V3622L10PQFG

更新时间: 2024-11-23 15:26:31
品牌 Logo 应用领域
艾迪悌 - IDT 时钟先进先出芯片内存集成电路
页数 文件大小 规格书
29页 262K
描述
Bi-Directional FIFO, 256X36, 6.5ns, Synchronous, CMOS, PQFP132, PLASTIC, QFP-132

72V3622L10PQFG 技术参数

是否无铅: 不含铅是否Rohs认证: 符合
生命周期:Obsolete零件包装代码:QFP
包装说明:QFP, SPQFP132,1.1SQ针数:132
Reach Compliance Code:compliantECCN代码:EAR99
HTS代码:8542.32.00.71风险等级:5.8
最长访问时间:6.5 ns其他特性:MAIL BOX BYPASS REGISTER
最大时钟频率 (fCLK):100 MHz周期时间:10 ns
JESD-30 代码:S-PQFP-G132JESD-609代码:e3
长度:24.13 mm内存密度:9216 bit
内存集成电路类型:BI-DIRECTIONAL FIFO内存宽度:36
功能数量:1端子数量:132
字数:256 words字数代码:256
工作模式:SYNCHRONOUS最高工作温度:70 °C
最低工作温度:组织:256X36
可输出:YES封装主体材料:PLASTIC/EPOXY
封装代码:QFP封装等效代码:SPQFP132,1.1SQ
封装形状:SQUARE封装形式:FLATPACK
并行/串行:PARALLEL峰值回流温度(摄氏度):260
电源:3.3 V认证状态:Not Qualified
座面最大高度:4.57 mm最大待机电流:0.005 A
子类别:FIFOs最大供电电压 (Vsup):3.45 V
最小供电电压 (Vsup):3.15 V标称供电电压 (Vsup):3.3 V
表面贴装:YES技术:CMOS
温度等级:COMMERCIAL端子面层:MATTE TIN
端子形式:GULL WING端子节距:0.635 mm
端子位置:QUAD处于峰值回流温度下的最长时间:30
宽度:24.13 mmBase Number Matches:1

72V3622L10PQFG 数据手册

 浏览型号72V3622L10PQFG的Datasheet PDF文件第2页浏览型号72V3622L10PQFG的Datasheet PDF文件第3页浏览型号72V3622L10PQFG的Datasheet PDF文件第4页浏览型号72V3622L10PQFG的Datasheet PDF文件第5页浏览型号72V3622L10PQFG的Datasheet PDF文件第6页浏览型号72V3622L10PQFG的Datasheet PDF文件第7页 
3.3 VOLT CMOS SyncBiFIFOTM  
256 x 36 x 2  
512 x 36 x 2  
IDT72V3622  
IDT72V3632  
IDT72V3642  
1,024 x 36 x 2  
Select IDT Standard timing (using EFA, EFB, FFA and FFB flags  
functions) or First Word Fall Through timing (using ORA, ORB, IRA  
and IRB flag functions)  
Available in 132-pin Plastic Quad Flatpack (PQFP) or space-saving  
120-pin Thin Quad Flatpack (TQFP)  
Functionally compatible to the 5V operating IDT723622/723632/  
723642  
Industrial temperature range (–40οC to +85οC) is available  
Green parts available, see ordering information  
FEATURES:  
Memory storage capacity:  
IDT72V3622  
IDT72V3632  
IDT72V3642  
256 x 36 x 2  
512 x 36 x 2  
1,024 x 36 x 2  
Supports clock frequencies up to 100 MHz  
Fast access times of 6.5ns  
Free-running CLKA and CLKB may be asynchronous or coincident  
(simultaneous reading and writing of data on a single clock edge  
is permitted)  
DESCRIPTION:  
Two independent clocked FIFOs buffering data in opposite direc-  
tions  
Mailbox bypass register for each FIFO  
Programmable Almost-Full and Almost-Empty flags  
Microprocessor Interface Control Logic  
FFA/IRA, EFA/ORA, AEA, and AFA flags synchronized by CLKA  
FFB/IRB, EFB/ORB, AEB, and AFB flags synchronized by CLKB  
TheIDT72V3622/72V3632/72V3642arefunctionallycompatibleversions  
of the IDT723622/723632/723642, designed to run off a 3.3V supply for  
exceptionally low-power consumption. These devices are monolithic, high-  
speed,low-power,CMOSBidirectionalSyncFIFO(clocked)memorieswhich  
supportclockfrequenciesupto100MHzandhavereadaccesstimesasfast  
as 6.5ns. Two independent 256/512/1,024 x 36 dual-port SRAM FIFOs on  
FUNCTIONAL BLOCK DIAGRAM  
MBF1  
Mail 1  
Register  
CLKA  
CSA  
Port-A  
Control  
Logic  
W/RA  
RAM  
ENA  
ARRAY  
MBA  
256 x 36  
512 x 36  
1,024 x 36  
36  
FIFO1,  
Mail1  
Reset  
Logic  
RST1  
Write  
Pointer  
Read  
Pointer  
36  
Status Flag  
Logic  
EFB/ORB  
AEB  
FFA/IRA  
AFA  
FIFO 1  
FS  
0
1
Programmable Flag  
Offset Registers  
Timing  
Mode  
FWFT  
FS  
A
0
- A35  
10  
B0 - B35  
FIFO 2  
Status Flag  
EFA/ORA  
FFB/IRB  
AFB  
Logic  
AEA  
36  
Read  
Pointer  
Write  
Pointer  
36  
FIFO2,  
Mail2  
Reset  
Logic  
RST2  
RAM  
ARRAY  
256 x 36  
512 x 36  
CLKB  
CSB  
W/RB  
Port-B  
Control  
Logic  
1,024 x 36  
ENB  
Mail 2  
Register  
MBB  
4660 drw 01  
MBF2  
CIDTOandMtheMIDTElogRoaCrereIgAisteLredtrTadeEmaMrkoPfInEtegRrateAdDTevUiceTRecEhnologRy,IAnc NSynGcBiEFIFOisatrademarkofIntegratedDeviceTechnology,Inc.  
FEBRUARY 2009  
1
©
2009 Integrated Device Technology, Inc. All rights reserved. Product specifications subject to change without notice.  
DSC-4660/6  

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