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72V3626L10PFG PDF预览

72V3626L10PFG

更新时间: 2024-11-23 19:53:03
品牌 Logo 应用领域
艾迪悌 - IDT 时钟先进先出芯片内存集成电路
页数 文件大小 规格书
36页 349K
描述
Bi-Directional FIFO, 256X36, 6.5ns, Synchronous, CMOS, PQFP128, GREEN, TQFP-128

72V3626L10PFG 技术参数

是否无铅:不含铅是否Rohs认证:符合
生命周期:Obsolete零件包装代码:QFP
包装说明:LFQFP, QFP128,.63X.87,20针数:128
Reach Compliance Code:compliantECCN代码:EAR99
HTS代码:8542.32.00.71风险等级:5.56
Is Samacsys:N最长访问时间:6.5 ns
其他特性:AUTO POWER DOWN; MAILBOX最大时钟频率 (fCLK):100 MHz
周期时间:10 nsJESD-30 代码:R-PQFP-G128
JESD-609代码:e3长度:20 mm
内存密度:9216 bit内存集成电路类型:BI-DIRECTIONAL FIFO
内存宽度:36湿度敏感等级:3
功能数量:1端子数量:128
字数:256 words字数代码:256
工作模式:SYNCHRONOUS最高工作温度:70 °C
最低工作温度:组织:256X36
可输出:YES封装主体材料:PLASTIC/EPOXY
封装代码:LFQFP封装等效代码:QFP128,.63X.87,20
封装形状:RECTANGULAR封装形式:FLATPACK, LOW PROFILE, FINE PITCH
并行/串行:PARALLEL峰值回流温度(摄氏度):260
电源:3.3 V认证状态:Not Qualified
座面最大高度:1.6 mm最大待机电流:0.001 A
子类别:FIFOs最大供电电压 (Vsup):3.45 V
最小供电电压 (Vsup):3.15 V标称供电电压 (Vsup):3.3 V
表面贴装:YES技术:CMOS
温度等级:COMMERCIAL端子面层:Matte Tin (Sn) - annealed
端子形式:GULL WING端子节距:0.5 mm
端子位置:QUAD处于峰值回流温度下的最长时间:30
宽度:14 mmBase Number Matches:1

72V3626L10PFG 数据手册

 浏览型号72V3626L10PFG的Datasheet PDF文件第2页浏览型号72V3626L10PFG的Datasheet PDF文件第3页浏览型号72V3626L10PFG的Datasheet PDF文件第4页浏览型号72V3626L10PFG的Datasheet PDF文件第5页浏览型号72V3626L10PFG的Datasheet PDF文件第6页浏览型号72V3626L10PFG的Datasheet PDF文件第7页 
3.3 VOLT CMOS TRIPLE BUS  
SyncFIFOTM WITH BUS-MATCHING  
256 x 36 x 2, 512 x 36 x 2,  
1,024 x 36 x 2  
IDT72V3626  
IDT72V3636  
IDT72V3646  
three default offsets (8, 16 and 64)  
Serial or parallel programming of partial flags  
Big- or Little-Endian format for word and byte bus sizes  
Master Reset clears data and configures FIFO, Partial Reset  
clears data but retains configuration settings  
FEATURES:  
Memory storage capacity:  
IDT72V3626–256 x 36 x 2  
IDT72V3636–512 x 36 x 2  
IDT72V3646–1,024 x 36 x 2  
Mailbox bypass registers for each FIFO  
Clock frequencies up to 100 MHz (6.5ns access time)  
Two independent FIFOs buffer data between one bidirectional  
36-bit port and two unidirectional 18-bit ports (Port C receives  
and Port B transmits)  
18-bit (word) and 9-bit (byte) bus sizing of 18 bits (word) on  
Ports B and C  
Select IDT Standard timing (using EFA, EFB, FFA, and FFC flag  
functions) or First Word Fall Through Timing (using ORA, ORB,  
IRA, and IRC flag functions)  
Free-running CLKA, CLKB and CLKC may be asynchronous or  
coincident (simultaneous reading and writing of data on a single  
clock edge is permitted)  
Auto power down minimizes power dissipation  
Available in a space-saving 128-pin Thin Quad Flatpack (TQFP)  
Pin and functionally compatible versions of 5V operating  
IDT723626/723636/723646  
Industrial temperature range (–40°C to +85°C) is available  
Green parts available, see ordering information  
Programmable Almost-Empty and Almost-Full flags; each has  
FUNCTIONAL BLOCK DIAGRAM  
MBF1  
Mail 1  
Register  
CLKA  
18  
CSA  
Port-A  
B0-B17  
W/RA  
ENA  
MBA  
Control  
RAM ARRAY  
36  
36  
Logic  
256 x 36  
512 x 36  
1,024 x 36  
CLKB  
RENB  
CSB  
Port-B  
Control  
Logic  
FIFO1,  
Mail1  
Reset  
Logic  
MRS1  
PRS1  
MBB  
Read  
Pointer  
Write  
Pointer  
SIZEB  
36  
Status Flag  
Logic  
FFA/IRA  
EFB/ORB  
AFA  
AEB  
FIFO1  
FIFO2  
Common  
Port  
SPM  
FS0/SD  
Control  
Logic  
Timing  
Mode  
BE  
Programmable Flag  
Offset Registers  
FS1/SEN  
(B and C)  
A -A35  
0
10  
FWFT  
FFC/IRC  
AFC  
Status Flag  
Logic  
EFA/ORA  
AEA  
Read  
Pointer  
Write  
Pointer  
FIFO2,  
Mail2  
Reset  
Logic  
MRS2  
PRS2  
36  
RAM ARRAY  
256 x 36  
18  
36  
36  
C -C17  
0
512 x 36  
1,024 x 36  
CLKC  
WENC  
MBC  
Port-C  
Control  
Logic  
Mail 2  
Register  
SIZEC  
4665 drw01  
MBF2  
IDTandtheIDTlogoareregisteredtrademarksofIntegratedDeviceTechnology,Inc. SyncFIFOisatrademarkofIntegratedDeviceTechnology,Inc.  
FEBRUARY 2009  
COMMERCIAL TEMPERATURE RANGE  
1
©
2009 Integrated Device Technology, Inc. All right reserved. Product specifications subject to change without notice.  
DSC-4665/6  

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