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72V3632L15PFG PDF预览

72V3632L15PFG

更新时间: 2024-11-26 19:50:03
品牌 Logo 应用领域
艾迪悌 - IDT 时钟先进先出芯片内存集成电路
页数 文件大小 规格书
29页 430K
描述
Bi-Directional FIFO, 512X36, 10ns, Synchronous, CMOS, PQFP120, GREEN, TQFP-120

72V3632L15PFG 技术参数

是否无铅: 不含铅是否Rohs认证: 符合
生命周期:Obsolete零件包装代码:QFP
包装说明:GREEN, TQFP-120针数:120
Reach Compliance Code:compliantECCN代码:EAR99
HTS代码:8542.32.00.71风险等级:5.79
最长访问时间:10 ns其他特性:MAIL BOX BYPASS REGISTER
最大时钟频率 (fCLK):66.7 MHz周期时间:15 ns
JESD-30 代码:S-PQFP-G120JESD-609代码:e3
长度:14 mm内存密度:18432 bit
内存集成电路类型:BI-DIRECTIONAL FIFO内存宽度:36
湿度敏感等级:3功能数量:1
端子数量:120字数:512 words
字数代码:512工作模式:SYNCHRONOUS
最高工作温度:70 °C最低工作温度:
组织:512X36可输出:YES
封装主体材料:PLASTIC/EPOXY封装代码:LFQFP
封装等效代码:QFP120,.63SQ,16封装形状:SQUARE
封装形式:FLATPACK, LOW PROFILE, FINE PITCH并行/串行:PARALLEL
峰值回流温度(摄氏度):260电源:3.3 V
认证状态:Not Qualified座面最大高度:1.6 mm
最大待机电流:0.005 A子类别:FIFOs
最大供电电压 (Vsup):3.6 V最小供电电压 (Vsup):3 V
标称供电电压 (Vsup):3.3 V表面贴装:YES
技术:CMOS温度等级:COMMERCIAL
端子面层:Matte Tin (Sn)端子形式:GULL WING
端子节距:0.4 mm端子位置:QUAD
处于峰值回流温度下的最长时间:30宽度:14 mm
Base Number Matches:1

72V3632L15PFG 数据手册

 浏览型号72V3632L15PFG的Datasheet PDF文件第2页浏览型号72V3632L15PFG的Datasheet PDF文件第3页浏览型号72V3632L15PFG的Datasheet PDF文件第4页浏览型号72V3632L15PFG的Datasheet PDF文件第5页浏览型号72V3632L15PFG的Datasheet PDF文件第6页浏览型号72V3632L15PFG的Datasheet PDF文件第7页 
3.3 VOLT CMOS SyncBiFIFOTM  
256 x 36 x 2  
512 x 36 x 2  
IDT72V3622  
IDT72V3632  
IDT72V3642  
1,024 x 36 x 2  
FFA/IRA, EFA/ORA, AEA, and AFA flags synchronized by CLKA  
FFB/IRB, EFB/ORB, AEB, and AFB flags synchronized by CLKB  
Select IDT Standard timing (using EFA, EFB, FFA and FFB flags  
functions) or First Word Fall Through timing (using ORA, ORB, IRA  
and IRB flag functions)  
FEATURES:  
Memory storage capacity:  
IDT72V3622  
IDT72V3632  
IDT72V3642  
256 x 36 x 2  
512 x 36 x 2  
1,024 x 36 x 2  
Available space-saving 120-pin Thin Quad Flatpack (TQFP)  
Functionally compatible to the 5V operating IDT723622/723632/  
723642  
Supports clock frequencies up to 100 MHz  
Fast access times of 6.5ns  
Free-running CLKA and CLKB may be asynchronous or coincident  
(simultaneous reading and writing of data on a single clock edge  
is permitted)  
Industrial temperature range (–40οC to +85οC) is available  
Green parts available, see ordering information  
Two independent clocked FIFOs buffering data in opposite direc-  
tions  
Mailbox bypass register for each FIFO  
Programmable Almost-Full and Almost-Empty flags  
Microprocessor Interface Control Logic  
DESCRIPTION:  
TheIDT72V3622/72V3632/72V3642arefunctionallycompatibleversions  
of the IDT723622/723632/723642, designed to run off a 3.3V supply for  
exceptionallylow-powerconsumption. Thesedevicesaremonolithic, high-  
FUNCTIONAL BLOCK DIAGRAM  
MBF1  
Mail 1  
Register  
CLKA  
CSA  
Port-A  
Control  
Logic  
W/RA  
RAM  
ENA  
ARRAY  
MBA  
256 x 36  
512 x 36  
1,024 x 36  
36  
FIFO1,  
Mail1  
Reset  
Logic  
RST1  
Write  
Pointer  
Read  
Pointer  
36  
Status Flag  
Logic  
EFB/ORB  
AEB  
FFA/IRA  
AFA  
FIFO 1  
FS  
0
1
Programmable Flag  
Offset Registers  
Timing  
Mode  
FWFT  
FS  
A
0
- A35  
10  
B0 - B35  
FIFO 2  
Status Flag  
EFA/ORA  
FFB/IRB  
AFB  
Logic  
AEA  
36  
Read  
Pointer  
Write  
Pointer  
36  
FIFO2,  
Mail2  
Reset  
Logic  
RST2  
RAM  
ARRAY  
256 x 36  
512 x 36  
CLKB  
CSB  
W/RB  
Port-B  
Control  
Logic  
1,024 x 36  
ENB  
Mail 2  
Register  
MBB  
4660 drw 01  
MBF2  
CIDTOandMtheMIDTElogRoaCrereIgAisteLredtrTadeEmaMrkoPfInEtegRrateAdDTevUiceTRecEhnologRy,IAnc NSynGcBiEFIFOisatrademarkofIntegratedDeviceTechnology,Inc.  
MAY 2013  
1
©
2013 Integrated Device Technology, Inc. All rights reserved. Product specifications subject to change without notice.  
DSC-4660/8  

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