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72V3633L10PFG PDF预览

72V3633L10PFG

更新时间: 2024-02-10 08:16:46
品牌 Logo 应用领域
艾迪悌 - IDT 先进先出芯片
页数 文件大小 规格书
28页 254K
描述
FIFO, 512X36, 6.5ns, Synchronous/Asynchronous, CMOS, PQFP128, GREEN, TQFP-128

72V3633L10PFG 技术参数

是否无铅: 不含铅是否Rohs认证: 符合
生命周期:Obsolete零件包装代码:QFP
包装说明:GREEN, TQFP-128针数:128
Reach Compliance Code:compliantECCN代码:EAR99
HTS代码:8542.32.00.71风险等级:5.84
最长访问时间:6.5 ns其他特性:MAILBOX
周期时间:10 nsJESD-30 代码:R-PQFP-G128
JESD-609代码:e3长度:20 mm
内存密度:18432 bit内存宽度:36
湿度敏感等级:3功能数量:1
端子数量:128字数:512 words
字数代码:512工作模式:SYNCHRONOUS/ASYNCHRONOUS
最高工作温度:70 °C最低工作温度:
组织:512X36可输出:YES
封装主体材料:PLASTIC/EPOXY封装代码:LQFP
封装形状:RECTANGULAR封装形式:FLATPACK, LOW PROFILE
并行/串行:PARALLEL峰值回流温度(摄氏度):260
座面最大高度:1.6 mm最大供电电压 (Vsup):3.6 V
最小供电电压 (Vsup):3 V标称供电电压 (Vsup):3.3 V
表面贴装:YES技术:CMOS
温度等级:COMMERCIAL端子面层:MATTE TIN
端子形式:GULL WING端子节距:0.65 mm
端子位置:QUAD处于峰值回流温度下的最长时间:30
宽度:14 mmBase Number Matches:1

72V3633L10PFG 数据手册

 浏览型号72V3633L10PFG的Datasheet PDF文件第2页浏览型号72V3633L10PFG的Datasheet PDF文件第3页浏览型号72V3633L10PFG的Datasheet PDF文件第4页浏览型号72V3633L10PFG的Datasheet PDF文件第5页浏览型号72V3633L10PFG的Datasheet PDF文件第6页浏览型号72V3633L10PFG的Datasheet PDF文件第7页 
3.3 VOLT CMOS SyncFIFOTM WITH  
BUS-MATCHING  
256 x 36 , 512 x 36  
1,024 x 36  
IDT72V3623  
IDT72V3633  
IDT72V3643  
Big- or Little-Endian format for word and byte bus sizes  
FEATURES:  
Reset clears data and configures FIFO, Partial Reset clears data  
but retains configuration settings  
Mailbox bypass registers for each FIFO  
Free-running CLKA and CLKB may be asynchronous or  
coincident (simultaneous reading and writing of data on a single  
clock edge is permitted)  
Memory storage capacity:  
IDT72V3623–256 x 36  
IDT72V3633–512 x 36  
IDT72V3643–1,024 x 36  
Clock frequencies up to 100 MHz (6.5 ns access time)  
Clocked FIFO buffering data from Port A to Port B  
IDT Standard timing (using EF and FF) or First Word Fall  
Through Timing (using OR and IR flag functions)  
Programmable Almost-Empty and Almost-Full flags; each has  
three default offsets (8, 16 and 64)  
Serial or parallel programming of partial flags  
Port B bus sizing of 36 bits (long word), 18 bits (word) and 9 bits  
(byte)  
Easily expandable in width and depth  
Auto power down minimizes power dissipation  
Available in a space-saving 128-pin Thin Quad Flatpack (TQFP)  
Pin and functionally compatible versions of the 5V operating  
IDT723623/723633/723643  
Industrial temperature range (–40°C to +85°C) is available  
Green parts available, see ordering information  
FUNCTIONAL BLOCK DIAGRAM  
MBF1  
Mail 1  
Register  
CLKA  
CSA  
Port-A  
W/RA  
Control  
ENA  
Logic  
MBA  
36  
RAM ARRAY  
36  
36  
FIFO1  
Mail1,  
Mail2,  
Reset  
Logic  
256 x 36  
512 x 36  
RS1  
RS2  
PRS  
1,024 x 36  
36  
Write  
Pointer  
Read  
Pointer  
A0-A35  
B0-B35  
Status Flag  
Logic  
EF/OR  
AE  
FF/IR  
AF  
36  
36  
SPM  
FS0/SD  
FS1/SEN  
Programmable Flag  
Offset Registers  
Timing  
Mode  
FWFT  
10  
CLKB  
CSB  
W/RB  
ENB  
MBB  
BE  
Port-B  
Control  
Logic  
BM  
SIZE  
Mail 2  
Register  
4662 drw01  
MBF2  
IDTandtheIDTlogoareregisteredtrademarkofIntegratedDeviceTechnology,Inc. SyncFIFOisatrademarkofIntegratedDeviceTechnology,Inc.  
MAY 2010  
COMMERCIAL TEMPERATURE RANGE  
1
©
2010 Integrated Device Technology, Inc. All rights reserved. Product specifications subject to change without notice.  
DSC-4662/6  

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