Datasheet > 72V3623

72V3623

更新时间： 2023-12-20 18:45:21

品牌	Logo	应用领域
瑞萨 - RENESAS		先进先出芯片
页数	文件大小	规格书
29页	360K
描述
256 x 36 SyncFIFO, 3.3V

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数据手册

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72V3623 数据手册

3.3 VOLT CMOS SyncFIFO^TMWITH

BUS-MATCHING

256 x 36

1,024 x 36

IDT72V3623

IDT72V3643

LEAD FINISH (SnPb) ARE IN EOL PROCESS - LAST TIME BUY EXPIRES JUNE 15, 2018

• Reset clears data and configures FIFO, Partial Reset clears

data but retains configuration settings

• Mailbox bypass registers for each FIFO

• Free-running CLKA and CLKB may be asynchronous or

coincident (simultaneous reading and writing of data on a single

clock edge is permitted)

FEATURES:

• Memory storage capacity:

IDT72V3623–256 x 36

IDT72V3643–1,024 x 36

• Clock frequencies up to 100 MHz (6.5 ns access time)

• Clocked FIFO buffering data from Port A to Port B

• IDT Standard timing (using EF and FF) or First Word Fall

Through Timing (using OR and IR flag functions)

• Programmable Almost-Empty and Almost-Full flags; each has

three default offsets (8, 16 and 64)

• Serial or parallel programming of partial flags

• Port B bus sizing of 36 bits (long word), 18 bits (word) and 9 bits

(byte)

• Easily expandable in width and depth

• Auto power down minimizes power dissipation

• Available in a space-saving 128-pin Thin Quad Flatpack (TQFP)

• Pin and functionally compatible versions of the 5V operating

IDT723623/723643

• Industrial temperature range (–40°C to +85°C) is available

• Green parts available, see ordering information

• Big- or Little-Endian format for word and byte bus sizes

FUNCTIONAL BLOCK DIAGRAM

MBF1

Mail 1

CLKA

CSA

Port-A

W/RA

Control

ENA

Logic

MBA

RAM ARRAY

FIFO1

RS1

RS2

PRS

256 x 36

1,024 x 36

Mail1,

Mail2,

Reset

Logic

Read

Pointer

Write

Pointer

A0-A35

B0-B35

Status Flag

Logic

EF/OR

A E

FF/IR

SPM

FS0/SD

FS1/SEN

Programmable Flag

Offset Registers

Timing

Mode

FWFT

CLKB

CSB

W/RB

ENB

MBB

Port-B

Control

Logic

SIZE

Mail 2

4662 drw01

MBF2

C^IDTO^andM^theM^IDTE^logR^oaC^rereI^gA^isteL^redtrT^adeE^maM^rkoP^fInE^tegR^rateA^dDT^evU^iceTR^ecE^hnologR^y,IA^nc.N^SyG^ncFE^{IFOisatrademarkofIntegratedDeviceTechnology,Inc.}

MARCH 2018

DSC-4662/8

12 3 4 5 6 7...29

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