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72V3624L10PF PDF预览

72V3624L10PF

更新时间: 2023-02-26 14:47:05
品牌 Logo 应用领域
艾迪悌 - IDT /
页数 文件大小 规格书
34页 285K
描述
TQFP-128, Tray

72V3624L10PF 数据手册

 浏览型号72V3624L10PF的Datasheet PDF文件第2页浏览型号72V3624L10PF的Datasheet PDF文件第3页浏览型号72V3624L10PF的Datasheet PDF文件第4页浏览型号72V3624L10PF的Datasheet PDF文件第5页浏览型号72V3624L10PF的Datasheet PDF文件第6页浏览型号72V3624L10PF的Datasheet PDF文件第7页 
3.3 VOLT CMOS SyncBiFIFOTM  
WITH BUS-MATCHING  
256 x 36 x 2  
IDT72V3624  
IDT72V3644  
1,024 x 36 x 2  
(byte)  
FEATURES:  
Memory storage capacity:  
Big- or Little-Endian format for word and byte bus sizes  
Master Reset clears data and configures FIFO, Partial Reset  
clears data but retains configuration settings  
IDT72V3624–256 x 36 x 2  
IDT72V3644–1,024 x 36 x 2  
Mailbox bypass registers for each FIFO  
Clock frequencies up to 100 MHz (6.5ns access time)  
Two independent clocked FIFOs buffering data in opposite  
directions  
Select IDT Standard timing (using EFA, EFB, FFA, and FFB  
flags functions) or First Word Fall Through Timing (using ORA,  
ORB, IRA, and IRB flag functions)  
Programmable Almost-Empty and Almost-Full flags; each has  
three default offsets (8, 16 and 64)  
Serial or parallel programming of partial flags  
Port B bus sizing of 36 bits (long word), 18 bits (word) and 9 bits  
Free-running CLKA and CLKB may be asynchronous or coinci-  
dent (simultaneous reading and writing of data on a single clock  
edge is permitted)  
Auto power down minimizes power dissipation  
Available in space saving 128-pin Thin Quad Flatpack (TQFP)  
Pin and functionally compatible version of the 5V operating  
IDT723624/723644  
Industrial temperature range (–40°C to +85°C) is available  
Green parts available, see ordering information  
FUNCTIONAL BLOCK DIAGRAM  
MBF1  
Mail 1  
Register  
CLKA  
Port-A  
Control  
Logic  
CSA  
W/RA  
ENA  
RAM ARRAY  
256 x 36  
1,024 x 36  
36  
36  
MBA  
36  
FIFO1,  
Mail1  
Reset  
Logic  
MRS1  
PRS  
1
Write  
Pointer  
Read  
Pointer  
36  
Status Flag  
Logic  
EFB/ORB  
AEB  
FFA/IRA  
AFA  
FIFO1  
FIFO2  
SPM  
FS0/SD  
Programmable Flag  
Offset Registers  
Timing  
Mode  
FWFT  
FS1/SEN  
A
0-A35  
B0-B35  
10  
EFA/ORA  
Status Flag  
Logic  
FFB/IR  
B
AFB  
AEA  
36  
Read  
Pointer  
Write  
Pointer  
36  
FIFO2,  
Mail2  
Reset  
Logic  
MRS2  
PRS  
2
RAM ARRAY  
256 x 36  
36  
36  
1,024 x 36  
CLKB  
CSB  
W/RB  
ENB  
MBB  
BE  
Port-B  
Control  
Logic  
Mail 2  
Register  
BM  
SIZE  
MBF2  
4664 drw01  
CIDTOandMtheMIDTElogRoaCrereIgAisteLredtrTadeEmaMrkoPfInEtegRrateAdDTevUiceTRecEhnologRy,IAnc.NSynGcBEiFIFOisatrademarkofIntegratedDeviceTechnology,Inc.  
MARCH 2015  
1
©
2015 Integrated Device Technology, Inc. All rights reserved. Product specifications subject to change without notice.  
DSC-4664/6  

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