Datasheet > 72V3626L10PF

72V3626L10PF

更新时间： 2023-05-15 00:00:00

品牌	Logo	应用领域
艾迪悌 - IDT		/
页数	文件大小	规格书
36页	349K
描述
TQFP-128, Tray

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数据手册

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72V3626L10PF 数据手册

3.3 VOLT CMOS TRIPLE BUS

SyncFIFO^TMWITH BUS-MATCHING

256 x 36 x 2, 512 x 36 x 2,

1,024 x 36 x 2

IDT72V3626

IDT72V3636

IDT72V3646

three default offsets (8, 16 and 64)

• Serial or parallel programming of partial flags

• Big- or Little-Endian format for word and byte bus sizes

• Master Reset clears data and configures FIFO, Partial Reset

clears data but retains configuration settings

FEATURES:

• Memory storage capacity:

IDT72V3626–256 x 36 x 2

IDT72V3636–512 x 36 x 2

IDT72V3646–1,024 x 36 x 2

• Mailbox bypass registers for each FIFO

• Clock frequencies up to 100 MHz (6.5ns access time)

• Two independent FIFOs buffer data between one bidirectional

36-bit port and two unidirectional 18-bit ports (Port C receives

and Port B transmits)

• 18-bit (word) and 9-bit (byte) bus sizing of 18 bits (word) on

Ports B and C

• Select IDT Standard timing (using EFA, EFB, FFA, and FFC flag

functions) or First Word Fall Through Timing (using ORA, ORB,

IRA, and IRC flag functions)

• Free-running CLKA, CLKB and CLKC may be asynchronous or

coincident (simultaneous reading and writing of data on a single

clock edge is permitted)

• Auto power down minimizes power dissipation

• Available in a space-saving 128-pin Thin Quad Flatpack (TQFP)

• Pin and functionally compatible versions of 5V operating

IDT723626/723636/723646

• Industrial temperature range (–40°C to +85°C) is available

• Green parts available, see ordering information

• Programmable Almost-Empty and Almost-Full flags; each has

FUNCTIONAL BLOCK DIAGRAM

MBF1

Mail 1

CLKA

CSA

Port-A

B0-B17

W/RA

ENA

MBA

Control

RAM ARRAY

Logic

256 x 36

512 x 36

1,024 x 36

CLKB

RENB

CSB

Port-B

Control

Logic

FIFO1,

Mail1

Reset

Logic

MRS1

PRS1

MBB

Read

Pointer

Write

Pointer

SIZEB

Status Flag

Logic

FFA/IRA

EFB/ORB

AFA

AEB

FIFO1

FIFO2

Common

Port

SPM

FS0/SD

Control

Logic

Timing

Mode

Programmable Flag

Offset Registers

FS1/SEN

(B and C)

A -A35

FWFT

FFC/IRC

AFC

Status Flag

Logic

EFA/ORA

AEA

Read

Pointer

Write

Pointer

FIFO2,

Mail2

Reset

Logic

MRS2

PRS2

RAM ARRAY

256 x 36

C -C17

512 x 36

1,024 x 36

CLKC

WENC

MBC

Port-C

Control

Logic

Mail 2

SIZEC

4665 drw01

MBF2

IDTandtheIDTlogoareregisteredtrademarksofIntegratedDeviceTechnology,Inc. SyncFIFOisatrademarkofIntegratedDeviceTechnology,Inc.

FEBRUARY 2009

COMMERCIAL TEMPERATURE RANGE

DSC-4665/6

12 3 4 5 6 7...36

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