3.3VOLTCMOSSyncBiFIFOTM WITH
BUS-MATCHINGANDBYTESWAPPING
64 x 36 x 2
IDT72V3614
• Three modes of byte-order swapping on port B
• Programmable Almost-Full and Almost-Empty flags
• Microprocessor interface control logic
FEATURES:
• Two independent clocked FIFOs (64 x 36 storage capacity each)
buffering data in opposite directions
• EFA , FFA , AEA , and AFA flags synchronized by CLKA
• EFB , FFB , AEB , and AFB flags synchronized by CLKB
• Passive parity checking on each port
• Parity generation can be selected for each port
• Available in 132-pin plastic quad flat package (PQF), or space
saving 120-pin thin quad flat package (TQFP)
• Pin and functionally compatible version of the 5V operating
IDT723614
• Supports clock frequencies up to 83 MHz
• Fast access times of 8 ns
• Free-running CLKA and CLKB can be asynchronous or coinci-
dent (simultaneous reading and writing of data on a single
clock edge is permitted)
• Mailbox bypass Register for each FIFO
• Dynamic Port B bus sizing of 36 bits (long word), 18 bits (word),
and 9 bits (byte)
• Selection of Big- or Little-Endian format for word and byte bus
sizes
• Industrial temperature range (–40°C to +85°C) is available
• Green parts available, see ordering information
FUNCTIONAL BLOCK DIAGRAM
CLKA
CSA
W/RA
ENA
Port-A
Control
Logic
MBF1
MBA
PEFB
Parity
Gen/Check
Mail 1
Register
PGB
RAM
ARRAY
36
64 x 36
RST
Device
Control
ODD/
EVEN
Read
Pointer
Write
Pointer
EFB
AEB
FFA
AFA
Status Flag
Logic
FIFO1
36
FS0
FS1
Programmable Flag
Offset Register
B0-B35
A0 - A35
FIFO2
FFB
AFB
EFA
AEA
Status Flag
Logic
Write
Pointer
Read
Pointer
36
RAM
ARRAY
64 x 36
PGA
Mail 2
Register
Parity
Gen/Check
PEFA
MBF2
CLKB
CSB
W/RB
ENB
BE
Port-B
Control
Logic
SIZ0
SIZ1
SW0
SW1
4663 drw 01
IDTandtheIDTlogoareregisteredtrademarksofIntegratedDeviceTechnology,Inc.SyncBiFIFOisatrademarkofIntegratedDeviceTechnology,Inc.
COMMERCIAL TEMPERATURE RANGE
FEBRUARY 2009
1
©2009 Integrated Device Technology, Inc. All rights reserved. Product specifications subject to change without notice.
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