Datasheet > 72V2101L10PF

72V2101L10PF

更新时间： 2024-09-16 09:15:59

品牌	Logo	应用领域
艾迪悌 - IDT		/
页数	文件大小	规格书
27页	256K
描述
TQFP-64, Tray

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数据手册
替代型号

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72V2101L10PF 数据手册

3.3 VOLT HIGH DENSITY CMOS

SUPERSYNC FIFO™

262,144 x 9

IDT72V2101

IDT72V2111

524,288 x 9

simultaneously)

• Available in the 64-pin Thin Quad Flat Pack (TQFP)

• High-performance submicron CMOS technology

FEATURES:

• Choose among the following memory organizations:

IDT72V2101

IDT72V2111

⎯

262,144 x 9

524,288 x 9

DESCRIPTION:

•

Pin-compatible with the IDT72V261/72V271 and the IDT72V281/

72V291 SuperSync FIFOs

The IDT72V2101/72V2111 are exceptionally deep, high speed, CMOS

First-In-First-Out(FIFO)memorieswithclockedreadandwritecontrols. These

FIFOs offer numerous improvements over previous SuperSync FIFOs,

includingthefollowing:

• 10ns read/write cycle time (6.5ns access time)

• Fixed, low first word data latency time

• 5V input tolerant

• Auto power down minimizes standby power consumption

• Master Reset clears entire FIFO

• Partial Reset clears data, but retains programmable settings

• Retransmit operation with fixed, low first word data latency time

• Empty, Full and Half-Full flags signal FIFO status

• Programmable Almost-Empty and Almost-Full flags, each flag can

default to one of two preselected offsets

• Program partial flags by either serial or parallel means

• SelectIDTStandardtiming(usingEFandFFflags)orFirstWordFall

Through timing (using OR and IR flags)

• Thelimitationofthefrequencyofoneclockinputwithrespecttotheotherhas

been removed. The Frequency Select pin (FS) has been removed, thus

itis nolongernecessarytoselectwhichofthe twoclockinputs, RCLKor

WCLK, is runningatthe higherfrequency.

• The period required by the retransmit operation is now fixed and short.

• Thefirstworddatalatencyperiod,fromthetimethefirstwordiswrittentoan

emptyFIFOtothetimeitcanberead,isnowfixedandshort. (Thevariable

clockcyclecountingdelayassociatedwiththelatencyperiodfound on

previousSuperSyncdeviceshasbeeneliminatedonthisSuperSyncfamily.)

SuperSyncFIFOsareparticularlyappropriatefornetwork,video,telecommu-

nications,datacommunicationsandotherapplicationsthatneedtobufferlarge

amountsofdata.

•

Output enable puts data outputs into high impedance state

• Easily expandable in depth and width

• Independent Read and Write clocks (permit reading and writing

FUNCTIONAL BLOCK DIAGRAM

D0 -D8

WEN

WCLK

SEN

OFFSET REGISTER

INPUT REGISTER

FF/IR

PAF

EF/OR

PAE

FLAG

LOGIC

WRITE CONTROL

LOGIC

RAM ARRAY

262,144 x 9

524,288 x 9

FWFT/SI

WRITE POINTER

READ POINTER

READ

CONTROL

LOGIC

OUTPUT REGISTER

MRS

PRS

RESET

LOGIC

RCLK

REN

Q0 -Q8

4669 drw 01

IDT and the IDT logo are trademarks of Integrated Device Technology, Inc. The SuperSync FIFO is a trademark of Integrated Device Technology, Inc.

DECEMBER 2008

COMMERCIAL AND INDUSTRIAL TEMPERATURE RANGES

DSC-4669/4

12 3 4 5 6 7...27

中文翻译

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72V2101L10PF 替代型号

型号	品牌	替代类型	描述	数据表
IDT72V2101L10PF	IDT	功能相似	3.3 VOLT HIGH DENSITY CMOS SUPERSYNC FIFO

与72V2101L10PF相关器件

型号	品牌	获取价格	描述	数据表
72V2101L10PFG	IDT	获取价格	3.3 VOLT HIGH DENSITY CMOS SUPERSYNC FIFO
72V2101L10PFG8	IDT	获取价格	3.3 VOLT HIGH DENSITY CMOS SUPERSYNC FIFO
72V2101L10PFGI	IDT	获取价格	3.3 VOLT HIGH DENSITY CMOS SUPERSYNC FIFO
72V2101L10PFGI8	IDT	获取价格	3.3 VOLT HIGH DENSITY CMOS SUPERSYNC FIFO
72V2101L15PF9	IDT	获取价格	FIFO, 256KX9, 10ns, Synchronous, CMOS, PQFP64, PLASTIC, TQFP-64
72V2101L15PFG	IDT	获取价格	3.3 VOLT HIGH DENSITY CMOS SUPERSYNC FIFO
72V2101L15PFG8	IDT	获取价格	3.3 VOLT HIGH DENSITY CMOS SUPERSYNC FIFO
72V2101L15PFGI	IDT	获取价格	3.3 VOLT HIGH DENSITY CMOS SUPERSYNC FIFO
72V2101L15PFGI8	IDT	获取价格	3.3 VOLT HIGH DENSITY CMOS SUPERSYNC FIFO
72V2101L15PFI8	IDT	获取价格	TQFP-64, Reel

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