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72V2103L10PFG8 PDF预览

72V2103L10PFG8

更新时间: 2024-11-07 00:22:11
品牌 Logo 应用领域
艾迪悌 - IDT 先进先出芯片
页数 文件大小 规格书
46页 541K
描述
3.3 VOLT HIGH-DENSITY SUPERSYNC II NARROW BUS FIFO

72V2103L10PFG8 数据手册

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3.3 VOLT HIGH-DENSITY SUPERSYNC II™  
NARROW BUS FIFO  
131,072 x 18/262,144 x 9  
262,144 x 18/524,288 x 9  
IDT72V2103  
IDT72V2113  
FEATURES:  
Empty, Full and Half-Full flags signal FIFO status  
Programmable Almost-Empty and Almost-Full flags, each flag can  
default to one of eight preselected offsets  
Selectable synchronous/asynchronous timing modes for Almost-  
Empty and Almost-Full flags  
Program programmable flags by either serial or parallel means  
Select IDT Standard timing (using EF and FF flags) or First Word  
Fall Through timing (using OR and IR flags)  
Output enable puts data outputs into high impedance state  
Easily expandable in depth and width  
JTAG port, provided for Boundary Scan function (BGA Only)  
Independent Read and Write Clocks (permit reading and writing  
simultaneously)  
Choose among the following memory organizations:  
IDT72V2103  
IDT72V2113  
131,072 x 18/262,144 x 9  
262,144 x 18/524,288 x 9  
Functionally compatible with the IDT72V255LA/72V265LA and  
IDT72V275/72V285 SuperSync FIFOs  
Up to 166 MHz Operation of the Clocks  
User selectable Asynchronous read and/or write ports (BGA Only)  
6 ns read/write cycle time (4.0 ns access time)  
User selectable input and output port bus-sizing  
- x9 in to x9 out  
- x9 in to x18 out  
- x18 in to x9 out  
- x18 in to x18 out  
Big-Endian/Little-Endian user selectable byte representation  
5V tolerant inputs  
Available in a 80-pin Thin Quad Flat Pack (TQFP) or a 100-pin Ball  
Grid Array (BGA) (with additional features)  
Pin compatible to the SuperSync II (IDT72V223/72V233/72V243/  
72V253/72V263/72V273/72V283/72V293)family  
Fixed, low first word latency  
Zero latency retransmit  
Auto power down minimizes standby power consumption  
Master Reset clears entire FIFO  
High-performance submicron CMOS technology  
Industrial temperature range (–40°C to +85°C) is available  
Green parts available, see ordering information  
Partial Reset clears data, but retains programmable settings  
FUNCTIONAL BLOCK DIAGRAM  
D0 -Dn (x9 or x18)  
LD SEN  
*Available on the  
WEN WCLK/WR  
*
BGA package only.  
INPUT REGISTER  
OFFSET REGISTER  
FF/IR  
PAF  
EF/OR  
PAE  
FLAG  
LOGIC  
WRITE CONTROL  
LOGIC  
ASYW  
HF  
*
RAM ARRAY  
FWFT/SI  
PFM  
131,072 x 18 or 262,144 x 9  
262,144 x 18 or 524,288 x 9  
FSEL0  
FSEL1  
WRITE POINTER  
READ POINTER  
BE  
CONTROL  
LOGIC  
IP  
RT  
RM  
ASYR  
READ  
CONTROL  
LOGIC  
OUTPUT REGISTER  
IW  
OW  
BUS  
*
CONFIGURATION  
MRS  
PRS  
RESET  
LOGIC  
RCLK/RD  
*
REN  
TCK  
*
*
TRST  
TMS  
TDI  
TDO  
JTAG CONTROL  
(BOUNDARY  
SCAN)  
*
6119 drw01  
*
Q0 -Qn (x9 or x18)  
OE  
*
*
IDTandtheIDTlogoareregisteredtrademarksofIntegratedDeviceTechnology,Inc.SuperSyncIIFIFOisatrademarkofIntegratedDeviceTechnology,Inc.  
COMMERCIAL AND INDUSTRIAL TEMPERATURE RANGES  
AUGUST 2014  
1
©
2014 Integrated Device Technology, Inc. All rights reserved. Product specifications subject to change without notice.  
DSC-6119/16  

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