Datasheet > 72V2101L20PFGI

72V2101L20PFGI

更新时间： 2024-11-07 00:43:07

品牌	Logo	应用领域
艾迪悌 - IDT		先进先出芯片
页数	文件大小	规格书
27页	434K
描述
3.3 VOLT HIGH DENSITY CMOS SUPERSYNC FIFO

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72V2101L20PFGI 数据手册

3.3 VOLT HIGH DENSITY CMOS

SUPERSYNC FIFO™

262,144 x 9

IDT72V2101

IDT72V2111

524,288 x 9

• Available in the 64-pin Thin Quad Flat Pack (TQFP)

FEATURES:

• High-performance submicron CMOS technology

• Industrial temperature range (–40°C to +85°C) is available

• Green parts available, see ordering information

• Choose among the following memory organizations:

IDT72V2101

IDT72V2111

⎯

262,144 x 9

524,288 x 9

•

Pin-compatible with the IDT72V261/72V271 and the IDT72V281/

72V291 SuperSync FIFOs

DESCRIPTION:

• 10ns read/write cycle time (6.5ns access time)

• Fixed, low first word data latency time

• 5V input tolerant

• Auto power down minimizes standby power consumption

• Master Reset clears entire FIFO

• Partial Reset clears data, but retains programmable settings

• Retransmit operation with fixed, low first word data latency time

• Empty, Full and Half-Full flags signal FIFO status

• Programmable Almost-Empty and Almost-Full flags, each flag can

default to one of two preselected offsets

• Program partial flags by either serial or parallel means

• Select IDT Standard timing (using EFand FFflags) or First Word Fall

Through timing (using OR and IR flags)

The IDT72V2101/72V2111 are exceptionally deep, high speed, CMOS

First-In-First-Out(FIFO)memorieswithclockedreadandwritecontrols. These

FIFOs offer numerous improvements over previous SuperSync FIFOs,

includingthefollowing:

• Thelimitationofthefrequencyofoneclockinputwithrespecttotheotherhas

been removed. The Frequency Select pin (FS) has been removed, thus

it is no longer necessary to select which of the two clock inputs, RCLK or

WCLK, is running at the higher frequency.

• The period required by the retransmit operation is now fixed and short.

• Thefirstworddatalatencyperiod,fromthetimethefirstwordiswrittentoan

emptyFIFOtothetimeitcanberead,isnowfixedandshort. (Thevariable

clockcyclecountingdelayassociatedwiththelatencyperiodfound on

previousSuperSyncdeviceshasbeeneliminatedonthisSuperSyncfamily.)

SuperSyncFIFOsareparticularlyappropriatefornetwork,video,telecommu-

nications,datacommunicationsandotherapplicationsthatneedtobufferlarge

amountsofdata.

•

Output enable puts data outputs into high impedance state

• Easily expandable in depth and width

• Independent Read and Write clocks (permit reading and writing

simultaneously)

FUNCTIONAL BLOCK DIAGRAM

D0 -D8

WEN

WCLK

SEN

OFFSET REGISTER

INPUT REGISTER

FF/IR

PAF

EF/OR

PAE

FLAG

LOGIC

WRITE CONTROL

LOGIC

RAM ARRAY

262,144 x 9

524,288 x 9

FWFT/SI

WRITE POINTER

READ POINTER

READ

CONTROL

LOGIC

OUTPUT REGISTER

MRS

PRS

RESET

LOGIC

RCLK

REN

Q0 -Q8

4669 drw 01

IDT and the IDT logo are trademarks of Integrated Device Technology, Inc. The SuperSync FIFO is a trademark of Integrated Device Technology, Inc.

JULY 2014

COMMERCIAL AND INDUSTRIAL TEMPERATURE RANGES

DSC-4669/5

12 3 4 5 6 7...27

中文翻译

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与72V2101L20PFGI相关器件

型号	品牌	获取价格	描述	数据表
72V2101L20PFGI8	IDT	获取价格	3.3 VOLT HIGH DENSITY CMOS SUPERSYNC FIFO
72V2103	RENESAS	获取价格	128K x 18 / 256K x 9 SuperSync II FIFO, 3.3V
72V2103L10BCG	IDT	获取价格	3.3 VOLT HIGH-DENSITY SUPERSYNC II NARROW BUS FIFO
72V2103L10BCG8	IDT	获取价格	3.3 VOLT HIGH-DENSITY SUPERSYNC II NARROW BUS FIFO
72V2103L10BCGI	IDT	获取价格	3.3 VOLT HIGH-DENSITY SUPERSYNC II NARROW BUS FIFO
72V2103L10BCGI8	IDT	获取价格	3.3 VOLT HIGH-DENSITY SUPERSYNC II NARROW BUS FIFO
72V2103L10PFG	IDT	获取价格	3.3 VOLT HIGH-DENSITY SUPERSYNC II NARROW BUS FIFO
72V2103L10PFG8	IDT	获取价格	3.3 VOLT HIGH-DENSITY SUPERSYNC II NARROW BUS FIFO
72V2103L10PFGI	IDT	获取价格	3.3 VOLT HIGH-DENSITY SUPERSYNC II NARROW BUS FIFO
72V2103L10PFGI8	IDT	获取价格	3.3 VOLT HIGH-DENSITY SUPERSYNC II NARROW BUS FIFO

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