Datasheet > 71V65803Z150PFGI

71V65803Z150PFGI

更新时间： 2024-11-09 00:23:27

品牌	Logo	应用领域
艾迪悌 - IDT		静态存储器
页数	文件大小	规格书
26页	368K
描述
3.3V Synchronous ZBT SRAMs

阅读下载

中文翻译

获取价格

数据手册

如果您发现信息不准确，欢迎纠错

71V65803Z150PFGI 数据手册

256K x 36, 512K x 18

3.3V Synchronous ZBT™ SRAMs

ZBT™ Feature

IDT71V65603/Z

IDT71V65803/Z

3.3V I/O, Burst Counter

Pipelined Outputs

AddressandcontrolsignalsareappliedtotheSRAMduringoneclock

cycle,andtwocycleslatertheassociateddatacycleoccurs,beitreadorwrite.

TheIDT71V65603/5803containdataI/O,addressandcontrolsignal

registers.Outputenableistheonlyasynchronoussignalandcanbeused

todisabletheoutputsatanygiventime.

A Clock Enable (CEN) pin allows operation of the IDT71V65603/5803

tobesuspendedaslongasnecessary.Allsynchronousinputsareignored

when(CEN)ishighandtheinternaldeviceregisterswillholdtheirprevious

values.

Therearethreechipenablepins(CE1, CE2, CE2)thatallowtheuser

to deselect the device when desired. If any one of these three are not

asserted when ADV/LD is low, no new memory operation can be

initiated. However, any pending data transfers (reads or writes) will be

completed. The data bus will tri-state two cycles after chip is deselected

or a write is initiated.

TheIDT71V65603/5803haveanon-chipburstcounter.Intheburst

mode, the IDT71V65603/5803 can provide four cycles of data for a

single address presented to the SRAM. The order of the burst

sequence is defined by the LBO input pin. The LBO pin selects

between linear and interleaved burst sequence. The ADV/LD signal is

used to load a new external address (ADV/LD = LOW) or increment

the internal burst counter (ADV/LD = HIGH).

Features

◆

256K x 36, 512K x 18 memory configurations

◆

Supports high performance system speed - 150MHz

(3.8ns Clock-to-Data Access)

◆

ZBT^TMFeature - No dead cycles between write and read cycles

◆

Internally synchronized output buffer enable eliminates the

need to control OE

Single R/W (READ/WRITE) control pin

Positive clock-edge triggered address, data, and control signal

◆

registers for fully pipelined applications

4-word burst capability (interleaved or linear)

Individual byte write (BW1 - BW4) control (May tie active)

Three chip enables for simple depth expansion

3.3V power supply (±5%)

3.3V I/O Supply (VDDQ)

Power down controlled by ZZ input

Packaged in a JEDEC standard 100-pin plastic thin quad

◆

flatpack (TQFP), 119 ball grid array (BGA) and 165 fine pitch

ball grid array(fBGA).

Description

The IDT71V65603/5803 are 3.3V high-speed 9,437,184-bit

(9Megabit)synchronousSRAMS.Theyaredesignedtoeliminatedeadbus

cycleswhenturningthebusaroundbetweenreadsandwrites, orwritesand

reads. Thus, they have been given the name ZBT^TM, or Zero Bus Turn-

around.

The IDT71V65603/5803 SRAM utilize IDT's latest high-performance

CMOS process, and are packaged in a JEDEC Standard 14mm x 20mm

100-pin thin plastic quad flatpack (TQFP) as well as a 119 ball grid array

(BGA) and 165 fine pitch ball grid array (fBGA) .

Pin Description Summary

0-A18

Address Inputs

Input

I/O

Synchronous

Asynchronous

Synchronous

N/A

Chip Enables

CE1

, CE

Output Enable

R/W

Read/Write Signal

Clock Enable

CEN

Individual Byte Write Selects

Clock

, BW

CLK

ADV/LD

LBO

Advance burst address / Load new address

Linear / Interleaved Burst Order

Sleep Mode

Synchronous

Static

Asynchronous

Synchronous

Static

I/O

-I/O31, I/OP1-I/OP4

Data Input / Output

Core Power, I/O Power

Ground

DD, VDDQ

Supply

Static

5304 tbl 01

ZBT and Zero Bus Turnaround are trademarks of Integrated Device Technology, Inc. and the architecture is supported by Micron Technology and Motorola, Inc.

OCTOBER 2008

DSC-5304/08

12 3 4 5 6 7...26

中文翻译

下载PDF

与71V65803Z150PFGI相关器件

型号	品牌	获取价格	描述	数据表
71V65903	RENESAS	获取价格	3.3V 512K x 18 ZBT Synchronous 3.3V I/O Flowthrough SRAM
71V65903S85PF8	IDT	获取价格	ZBT SRAM, 512KX18, 8.5ns, CMOS, PQFP100, 14 X 20 MM, 1.40 MM HEIGHT, MO-136DJ, PLASTIC, TQ
71V67602	RENESAS	获取价格	3.3V 256K x 36 Synchronous 2.5V I/O PipeLined SRAM
71V67602133PFG	IDT	获取价格	Cache SRAM
71V67602133PFGI	IDT	获取价格	Cache SRAM
71V67602S133BG	IDT	获取价格	Cache SRAM, 256KX36, 4.2ns, CMOS, PBGA119, 14 X 22 MM, PLASTIC, MS-028AA, BGA-119
71V67602S133BGG	IDT	获取价格	PBGA-119, Tray
71V67602S133BGG8	IDT	获取价格	PBGA-119, Reel
71V67602S133BGI	IDT	获取价格	Cache SRAM, 256KX36, 4.2ns, CMOS, PBGA119, 14 X 22 MM, PLASTIC, MS-028AA, BGA-119
71V67602S133BQG	IDT	获取价格	Cache SRAM, 256KX36, 4.2ns, CMOS, PBGA165, 13 X 15 MM, GREEN, FBGA-165

与71V65803Z150PFGI相关文章

英伟达新AI芯片Rubin或提前半年亮相
2024-11-05

19
苹果iPhone 17将全系采用三星/LG显示LTPO OLED面板
2024-11-05

17
三星深化印度制造布局，供应链本地化进程加速
2024-10-29

39
芯擎科技“星辰一号”自动驾驶芯片点亮成功，2025年量产在即
2024-10-29

37

产品中心

服务支持

精选活动

关于我们

帮助中心

71V65803Z150PFGI

71V65803Z150PFGI 数据手册

与71V65803Z150PFGI相关器件

与71V65803Z150PFGI相关文章

您还可以找

产品中心

服务支持

精选活动

关于我们

帮助中心

71V65803Z150PFGI

71V65803Z150PFGI 数据手册

与71V65803Z150PFGI相关器件

与71V65803Z150PFGI相关文章

您还可以找

您在本页遇到什么问题？