Datasheet > 71V67602

71V67602

更新时间： 2024-09-20 14:57:55

品牌	Logo	应用领域
瑞萨 - RENESAS		静态存储器
页数	文件大小	规格书
24页	534K
描述
3.3V 256K x 36 Synchronous 2.5V I/O PipeLined SRAM

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数据手册

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71V67602 数据手册

256K X 36, 512K X 18

3.3VSynchronousSRAMs

2.5V I/O, Burst Counter

IDT71V67602

IDT71V67802

PipelinedOutputs,SingleCycleDeselect

Features

Description

◆

256K x 36, 512K x 18 memory configurations

Supports high system speed:

The IDT71V67602/7802 are high-speed SRAMs organized as

256K x 36/512K x 18. The IDT71V676/78 SRAMs contain write, data,

addressandcontrolregisters. InternallogicallowstheSRAMtogenerate

aself-timedwritebaseduponadecisionwhichcanbeleftuntiltheendof

thewritecycle.

◆

– 166MHz 3.5ns clock access time

– 150MHz 3.8ns clock access time

– 133MHz 4.2ns clock access time

◆

LBO input selects interleaved or linear burst mode

Self-timed write cycle with global write control (GW), byte

write enable (BWE), and byte writes (BWx)

3.3V core power supply

Power down controlled by ZZ input

2.5V I/O supply (VDDQ)

Packaged in a JEDEC Standard 100-pin plastic thin quad

flatpack (TQFP), 119 ball grid array (BGA) and 165 fine pitch

ball grid array.

Theburstmodefeatureoffersthehighestlevelofperformancetothe

systemdesigner,astheIDT71V67602/7802canprovidefourcyclesof

dataforasingleaddresspresentedtotheSRAM. Aninternalburstaddress

counteracceptsthefirstcycleaddressfromtheprocessor,initiatingthe

accesssequence.Thefirstcycleofoutputdatawillbepipelinedforone

cycle before it is available on the next rising clock edge. If burst mode

operationisselected(ADV=LOW),thesubsequentthreecyclesofoutput

datawillbeavailabletotheuseronthenextthreerisingclockedges. The

orderofthesethreeaddressesaredefinedbytheinternalburstcounter

and the LBO input pin.

◆

TheIDT71V67602/7802SRAMsutilizeIDT’slatesthigh-performance

CMOSprocessandarepackagedinaJEDECstandard14mmx20mm

100-pinthinplasticquadflatpack(TQFP)aswellasa119ballgridarray

(BGA) and 165 fine pitch ball grid array (fBGA).

PinDescriptionSummary

0-A18

Address Inputs

Input

I/O

Synchronous

Asynchronous

Synchronous

N/A

Chip Enable

, CS

Chip Selects

Output Enable

Global Write Enable

Byte Write Enable

Individual Byte Write Selects

Clock

BWE

BW , BW

(1)

, BW

CLK

Burst Address Advance

Address Status (Cache Controller)

Address Status (Processor)

Linear / Interleaved Burst Order

Sleep Mode

Synchronous

ADV

ADSC

ADSP

LBO

Asynchronous

Synchronous

N/A

I/O

-I/O31, I/OP1-I/OP4

Data Input / Output

Core Power, I/O Power

Ground

DD, VDDQ

Supply

N/A

5311 tbl 01

NOTE:

1. BW3 and BW4 are not applicable for the IDT71V67802.

FEBRUARY2009

DSC-5311/09

12 3 4 5 6 7...24

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与71V67602相关器件

型号	品牌	获取价格	描述	数据表
71V67602133PFG	IDT	获取价格	Cache SRAM
71V67602133PFGI	IDT	获取价格	Cache SRAM
71V67602S133BG	IDT	获取价格	Cache SRAM, 256KX36, 4.2ns, CMOS, PBGA119, 14 X 22 MM, PLASTIC, MS-028AA, BGA-119
71V67602S133BGG	IDT	获取价格	PBGA-119, Tray
71V67602S133BGG8	IDT	获取价格	PBGA-119, Reel
71V67602S133BGI	IDT	获取价格	Cache SRAM, 256KX36, 4.2ns, CMOS, PBGA119, 14 X 22 MM, PLASTIC, MS-028AA, BGA-119
71V67602S133BQG	IDT	获取价格	Cache SRAM, 256KX36, 4.2ns, CMOS, PBGA165, 13 X 15 MM, GREEN, FBGA-165
71V67602S133BQG8	IDT	获取价格	SRAM
71V67602S133PFGI	IDT	获取价格	TQFP-100, Tray
71V67602S133PFGI8	IDT	获取价格	TQFP-100, Reel

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