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71V65603Z150BGG PDF预览

71V65603Z150BGG

更新时间： 2024-02-28 07:22:26
品牌 Logo 应用领域
艾迪悌 - IDT 静态存储器内存集成电路
页数 文件大小 规格书
26页 368K
描述
3.3V Synchronous ZBT SRAMs

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71V65603Z150BGG 技术参数

是否Rohs认证： 符合生命周期：Active
包装说明：BGA,Reach Compliance Code：compliant
HTS代码：8542.32.00.41风险等级：5.64
最长访问时间：3.8 ns其他特性：PIPELINED ARCHITECTURE
JESD-30 代码：R-PBGA-B119长度：22 mm
内存密度：9437184 bit内存集成电路类型：ZBT SRAM
内存宽度：36功能数量：1
端子数量：119字数：262144 words
字数代码：256000工作模式：SYNCHRONOUS
最高工作温度：70 °C最低工作温度：
组织：256KX36封装主体材料：PLASTIC/EPOXY
封装代码：BGA封装形状：RECTANGULAR
封装形式：GRID ARRAY并行/串行：PARALLEL
峰值回流温度（摄氏度）：260座面最大高度：2.36 mm
最大供电电压 (Vsup)：3.465 V最小供电电压 (Vsup)：3.135 V
标称供电电压 (Vsup)：3.3 V表面贴装：YES
技术：CMOS温度等级：COMMERCIAL
端子形式：BALL端子节距：1.27 mm
端子位置：BOTTOM处于峰值回流温度下的最长时间：30
宽度：14 mm

71V65603Z150BGG 数据手册

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256K x 36, 512K x 18  
3.3V Synchronous ZBT™ SRAMs  
ZBT™ Feature  
IDT71V65603/Z  
IDT71V65803/Z  
3.3V I/O, Burst Counter  
Pipelined Outputs  
AddressandcontrolsignalsareappliedtotheSRAMduringoneclock  
cycle,andtwocycleslatertheassociateddatacycleoccurs,beitreadorwrite.  
TheIDT71V65603/5803containdataI/O,addressandcontrolsignal  
registers.Outputenableistheonlyasynchronoussignalandcanbeused  
todisabletheoutputsatanygiventime.  
A Clock Enable (CEN) pin allows operation of the IDT71V65603/5803  
tobesuspendedaslongasnecessary.Allsynchronousinputsareignored  
when(CEN)ishighandtheinternaldeviceregisterswillholdtheirprevious  
values.  
Therearethreechipenablepins(CE1, CE2, CE2)thatallowtheuser  
to deselect the device when desired. If any one of these three are not  
asserted when ADV/LD is low, no new memory operation can be  
initiated. However, any pending data transfers (reads or writes) will be  
completed. The data bus will tri-state two cycles after chip is deselected  
or a write is initiated.  
TheIDT71V65603/5803haveanon-chipburstcounter.Intheburst  
mode, the IDT71V65603/5803 can provide four cycles of data for a  
single address presented to the SRAM. The order of the burst  
sequence is defined by the LBO input pin. The LBO pin selects  
between linear and interleaved burst sequence. The ADV/LD signal is  
used to load a new external address (ADV/LD = LOW) or increment  
the internal burst counter (ADV/LD = HIGH).  
Features  
◆
256K x 36, 512K x 18 memory configurations  
◆
Supports high performance system speed - 150MHz  
(3.8ns Clock-to-Data Access)  
◆
ZBTTM Feature - No dead cycles between write and read cycles  
◆
Internally synchronized output buffer enable eliminates the  
need to control OE  
Single R/W (READ/WRITE) control pin  
Positive clock-edge triggered address, data, and control signal  
◆
◆
registers for fully pipelined applications  
4-word burst capability (interleaved or linear)  
Individual byte write (BW1 - BW4) control (May tie active)  
Three chip enables for simple depth expansion  
3.3V power supply (±5%)  
3.3V I/O Supply (VDDQ)  
Power down controlled by ZZ input  
Packaged in a JEDEC standard 100-pin plastic thin quad  
◆
◆
◆
◆
◆
◆
◆
flatpack (TQFP), 119 ball grid array (BGA) and 165 fine pitch  
ball grid array(fBGA).  
Description  
The IDT71V65603/5803 are 3.3V high-speed 9,437,184-bit  
(9Megabit)synchronousSRAMS.Theyaredesignedtoeliminatedeadbus  
cycleswhenturningthebusaroundbetweenreadsandwrites, orwritesand  
reads. Thus, they have been given the name ZBTTM, or Zero Bus Turn-  
around.  
The IDT71V65603/5803 SRAM utilize IDT's latest high-performance  
CMOS process, and are packaged in a JEDEC Standard 14mm x 20mm  
100-pin thin plastic quad flatpack (TQFP) as well as a 119 ball grid array  
(BGA) and 165 fine pitch ball grid array (fBGA) .  
Pin Description Summary  
A
0-A18  
Address Inputs  
Input  
Input  
Input  
Input  
Input  
Input  
Input  
Input  
Input  
Input  
I/O  
Synchronous  
Synchronous  
Asynchronous  
Synchronous  
Synchronous  
Synchronous  
N/A  
Chip Enables  
CE1  
, CE  
2
, CE  
2
Output Enable  
OE  
R/W  
Read/Write Signal  
Clock Enable  
CEN  
Individual Byte Write Selects  
Clock  
BW  
1
, BW  
2
, BW  
3
, BW  
4
CLK  
ADV/LD  
LBO  
Advance burst address / Load new address  
Linear / Interleaved Burst Order  
Sleep Mode  
Synchronous  
Static  
ZZ  
Asynchronous  
Synchronous  
Static  
I/O  
0
-I/O31, I/OP1-I/OP4  
Data Input / Output  
Core Power, I/O Power  
Ground  
V
V
DD, VDDQ  
SS  
Supply  
Supply  
Static  
5304 tbl 01  
ZBT and Zero Bus Turnaround are trademarks of Integrated Device Technology, Inc. and the architecture is supported by Micron Technology and Motorola, Inc.  
OCTOBER 2008  
1
©2008 Integrated Device Technology, Inc.  
DSC-5304/08  
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