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71V65603ZS133BQGI PDF预览

71V65603ZS133BQGI

更新时间: 2024-12-02 07:21:23
品牌 Logo 应用领域
艾迪悌 - IDT 静态存储器
页数 文件大小 规格书
26页 440K
描述
ZBT SRAM, 256KX36, 4.2ns, CMOS, PBGA165

71V65603ZS133BQGI 数据手册

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256K x 36, 512K x 18  
3.3V Synchronous ZBT™ SRAMs  
ZBTFeature  
IDT71V65603/Z  
IDT71V65803/Z  
3.3V I/O, Burst Counter  
PipelinedOutputs  
Features  
AddressandcontrolsignalsareappliedtotheSRAMduringoneclock  
cycle,andtwocycleslatertheassociateddatacycleoccurs,beitreadorwrite.  
TheIDT71V65603/5803containdataI/O,addressandcontrolsignal  
registers.Outputenableistheonlyasynchronoussignalandcanbeused  
todisabletheoutputsatanygiventime.  
256K x 36, 512K x 18 memory configurations  
Supports high performance system speed - 150MHz  
(3.8ns Clock-to-Data Access)  
ZBTTM Feature - No dead cycles between write and read cycles  
Internally synchronized output buffer enable eliminates the  
AClockEnable(CEN)pinallowsoperationoftheIDT71V65603/5803to  
besuspendedaslongasnecessary.Allsynchronousinputsareignoredwhen  
(CEN)ishighandtheinternaldeviceregisterswillholdtheirpreviousvalues.  
Therearethreechipenablepins(CE1, CE2, CE2)thatallowtheuser  
todeselectthedevicewhendesired.Ifanyoneofthesethreearenotasserted  
whenADV/LDislow,nonewmemoryoperationcanbeinitiated.However,  
anypendingdatatransfers(readsorwrites)willbecompleted.Thedatabus  
willtri-statetwocyclesafterchipisdeselectedorawriteisinitiated.  
TheIDT71V65603/5803haveanon-chipburstcounter.Intheburst  
mode,theIDT71V65603/5803canprovidefourcyclesofdataforasingle  
address presented to the SRAM. The order of the burst sequence is  
defined by the LBO input pin. The LBO pin selects between linear and  
interleaved burst sequence. The ADV/LDsignal is used to load a new  
externaladdress(ADV/LD=LOW) orincrementtheinternalburstcounter  
(ADV/LD = HIGH).  
need to control OE  
Single R/W (READ/WRITE) control pin  
Positive clock-edge triggered address, data, and control  
signal registers for fully pipelined applications  
4-word burst capability (interleaved or linear)  
Individual byte write (BW1 - BW4) control (May tie active)  
Three chip enables for simple depth expansion  
3.3V power supply (±5%)  
3.3V I/O Supply (VDDQ)  
Power down controlled by ZZ input  
Packaged in a JEDEC standard 100-pin plastic thin quad  
flatpack (TQFP), 119 ball grid array (BGA) and 165 fine pitch  
ball grid array(fBGA).  
Description  
The IDT71V65603/5803 are 3.3V high-speed 9,437,184-bit  
(9Megabit)synchronousSRAMS.Theyaredesignedtoeliminatedeadbus  
cycleswhenturningthebusaroundbetweenreadsandwrites, orwritesand  
reads.Thus,theyhavebeengiventhenameZBTTM,orZeroBusTurnaround.  
The IDT71V65603/5803 SRAM utilize IDT's latest high-performance  
CMOSprocess,andarepackagedinaJEDECStandard14mmx20mm100-  
pinthinplasticquadflatpack(TQFP)aswellasa119ballgridarray(BGA)and  
165 fine pitch ball grid array (fBGA) .  
PinDescriptionSummary  
A
0-A18  
Address Inputs  
Input  
Input  
Input  
Input  
Input  
Input  
Input  
Input  
Input  
Input  
I/O  
Synchronous  
Synchronous  
Asynchronous  
Synchronous  
Synchronous  
Synchronous  
N/A  
Chip Enables  
CE1  
, CE  
2
, CE  
2
Output Enable  
OE  
R/W  
Read/Write Signal  
Clock Enable  
CEN  
Individual Byte Write Selects  
Clock  
BW  
1
, BW  
2
, BW  
3
, BW  
4
CLK  
ADV/LD  
LBO  
Advance burst address / Load new address  
Linear / Interleaved Burst Order  
Sleep Mode  
Synchronous  
Static  
ZZ  
Asynchronous  
Synchronous  
Static  
I/O  
0
-I/O31, I/OP1-I/OP4  
Data Input / Output  
Core Power, I/O Power  
Ground  
V
V
DD, VDDQ  
SS  
Supply  
Supply  
Static  
5304 tbl 01  
ZBT and Zero Bus Turnaround are trademarks of Integrated Device Technology, Inc. and the architecture is supported by Micron Technology and Motorola, Inc.  
FEBRUARY 2007  
1
©2007IntegratedDeviceTechnology,Inc.  
DSC-5304/07  

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