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71V65703 PDF预览

71V65703

更新时间: 2024-12-02 14:57:55
品牌 Logo 应用领域
瑞萨 - RENESAS 静态存储器
页数 文件大小 规格书
27页 306K
描述
3.3V 256K x 36 ZBT Synchronous 3.3V I/O Flowthrough SRAM

71V65703 数据手册

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256K x 36, 512K x 18  
71V65703  
71V65903  
3.3VSynchronousZBTSRAMs  
3.3V I/O, Burst Counter  
Flow-Through Outputs  
Features  
Three chip enables for simple depth expansion  
3.3V power supply (±5%)  
3.3V (±5%) I/O Supply (VDDQ)  
Power down controlled by ZZ input  
Packaged in a JEDEC standard 100-pin plastic thin quad  
flatpack (TQFP), 119 ball grid array (BGA) and 165 fine pitch  
ball grid array (fBGA)  
Industrial temperature range (–40°C to +85°C) is available  
for selected speeds  
256K x 36, 512K x 18 memory configurations  
Supports high performance system speed - 100 MHz  
(7.5 ns Clock-to-Data Access)  
ZBTTM Feature - No dead cycles between write and read  
cycles  
Internally synchronized output buffer enable eliminates the  
need to control OE  
Single R/W (READ/WRITE) control pin  
4-word burst capability (Interleaved or linear)  
Individual byte write (BW1 - BW4) control (May tie active)  
Green parts available, see ordering information  
Functional Block Diagram — 256K x 36  
256K x 36 BIT  
MEMORY ARRAY  
Address  
LBO  
Address A [0:17]  
D
D
Q
Q
CE1, CE2, CE2  
R/W  
Control  
CEN  
ADV/LD  
BWx  
DI  
DO  
D
Q
Control Logic  
Clk  
Mux  
Sel  
Clock  
Gate  
OE  
Data I/O [0:31], I/O P[1:4]  
,
5298 drw 01  
ZBT and Zero Bus Turnaround are trademarks of Renesas Electronics Corporation and the architecture is supported by Micron Technology and Motorola, Inc.  
1
Oct.18.21  

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