256K x 36, 512K x 18
IDT71V65602/Z
IDT71V65802/Z
3.3VSynchronousZBT™SRAMs
2.5V I/O, Burst Counter
PipelinedOutputs
Features
AddressandcontrolsignalsareappliedtotheSRAMduringoneclock
cycle,andtwocycleslatertheassociateddatacycleoccurs,beitreadorwrite.
The IDT71V65602/5802 contain data I/O, address and control signal
registers.Outputenableistheonlyasynchronoussignalandcanbeusedto
disabletheoutputsatanygiventime.
A Clock Enable (CEN) pin allows operation of the IDT71V65602/5802
tobesuspendedaslongasnecessary.Allsynchronousinputsareignored
when(CEN)ishighandtheinternaldeviceregisterswillholdtheirprevious
values.
◆
256K x 36, 512K x 18 memory configurations
◆
Supports high performance system speed - 150MHz
(3.8ns Clock-to-Data Access)
◆
ZBTTM Feature - No dead cycles between write and read cycles
◆
Internally synchronized output buffer enable eliminates the
need to control OE
Single R/W (READ/WRITE) control pin
Positive clock-edge triggered address, data, and control
◆
◆
There are three chip enable pins (CE1, CE2, CE2) that allow the
user to deselect the device when desired. If any one of these three are not
asserted when ADV/LDis low, no new memory operation can be initiated.
However,anypendingdatatransfers(readsorwrites)willbecompleted.The
databuswilltri-statetwocyclesafterchipisdeselectedorawriteisinitiated.
The IDT71V65602/5802 have an on-chip burst counter. In the burst
mode, the IDT71V65602/5802 can provide four cycles of data for a single
addresspresentedtotheSRAM.Theorderoftheburstsequenceisdefined
bytheLBOinputpin.TheLBOpinselectsbetweenlinearandinterleavedburst
sequence.TheADV/LDsignalisusedtoloadanewexternaladdress(ADV/
LD=LOW) orincrementtheinternalburstcounter(ADV/LD=HIGH).
The IDT71V65602/5802 SRAM utilize IDT's latest high-performance
signal registers for fully pipelined applications
4-word burst capability (interleaved or linear)
Individual byte write (BW1 - BW4) control (May tie active)
Three chip enables for simple depth expansion
3.3V power supply (±5%)
2.5V I/O Supply (VDDQ)
Power down controlled by ZZ input
Packaged in a JEDEC standard 100-pin plastic thin quad and
◆
◆
◆
◆
◆
◆
◆
flatpack (TQFP), 119 ball grid array (BGA) and 165 fine pitch
ball grid array (fBGA)
Description
The IDT71V65602/5802 are 3.3V high-speed 9,437,184-bit CMOSprocess,andarepackagedinaJEDECStandard14mmx20mm100-
(9Megabit)synchronousSRAMs.Theyaredesignedtoeliminatedead
bus cycles when turning the bus around between reads and writes, or
writesandreads. Thus, theyhavebeengiventhenameZBTTM, orZero
Bus Turnaround.
pin thin plastic quad flatpack (TQFP) as well as a 119 ball grid array (BGA)
and a 165 fine pitch ball grid array (fBGA).
PinDescriptionSummary
A
0
-A18
Address Inputs
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
I/O
Synchronous
Synchronous
Asynchronous
Synchronous
Synchronous
Synchronous
N/A
Chip Enables
CE
1, CE
2
, CE
2
Output Enable
OE
R/W
Read/Write Signal
Clock Enable
CEN
Individual Byte Write Selects
Clock
BW
1, BW
2
, BW
3
, BW
4
CLK
ADV/LD
Advance burst address / Load new address
Linear / Interleaved Burst Order
Sleep Mode
Synchronous
Static
LBO
ZZ
Asynchronous
Synchronous
Static
I/O
0-I/O31, I/OP1-I/OP4
Data Input / Output
Core Power, I/O Power
Ground
V
V
DD, VDDQ
SS
Supply
Supply
Static
5303 tbl 01
ZBT and Zero Bus Turnaround are trademarks of Integrated Device Technology, Inc. and the architecture is supported by Micron Technology and Motorola, Inc.
FEBRUARY 2009
1
©2007IntegratedDeviceTechnology,Inc.
DSC-5303/06
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