5秒后页面跳转
71V65802S133PFG PDF预览

71V65802S133PFG

更新时间: 2024-12-01 15:40:43
品牌 Logo 应用领域
艾迪悌 - IDT /
页数 文件大小 规格书
26页 970K
描述
TQFP-100, Tray

71V65802S133PFG 技术参数

是否无铅:不含铅是否Rohs认证:符合
生命周期:Obsolete零件包装代码:TQFP
包装说明:LQFP,针数:100
Reach Compliance Code:compliantECCN代码:3A991.B.2.A
HTS代码:8542.32.00.41风险等级:5.84
Is Samacsys:NBase Number Matches:1

71V65802S133PFG 数据手册

 浏览型号71V65802S133PFG的Datasheet PDF文件第2页浏览型号71V65802S133PFG的Datasheet PDF文件第3页浏览型号71V65802S133PFG的Datasheet PDF文件第4页浏览型号71V65802S133PFG的Datasheet PDF文件第5页浏览型号71V65802S133PFG的Datasheet PDF文件第6页浏览型号71V65802S133PFG的Datasheet PDF文件第7页 
256K x 36, 512K x 18  
IDT71V65602  
IDT71V65802  
3.3VSynchronousZBTSRAMs  
2.5V I/O, Burst Counter  
PipelinedOutputs  
Features  
AddressandcontrolsignalsareappliedtotheSRAMduringoneclock  
cycle,andtwocycleslatertheassociateddatacycleoccurs,beitreadorwrite.  
The IDT71V65602/5802 contain data I/O, address and control signal  
registers.Outputenableistheonlyasynchronoussignalandcanbeusedto  
disabletheoutputsatanygiventime.  
A Clock Enable (CEN) pin allows operation of the IDT71V65602/5802  
tobesuspendedaslongasnecessary.Allsynchronousinputsareignored  
when(CEN)ishighandtheinternaldeviceregisterswillholdtheirprevious  
values.  
There are three chip enable pins (CE1, CE2, CE2) that allow the  
usertodeselectthedevicewhendesired. Ifanyoneofthesethreearenot  
assertedwhenADV/LDislow, nonewmemoryoperationcanbeinitiated.  
However,anypendingdatatransfers(readsorwrites)willbecompleted.The  
databuswilltri-statetwocyclesafterchipisdeselectedorawriteisinitiated.  
The IDT71V65602/5802 have an on-chip burst counter. In the burst  
mode, the IDT71V65602/5802 can provide four cycles of data for a single  
addresspresentedtotheSRAM.Theorderoftheburstsequenceisdefined  
bytheLBOinputpin.TheLBOpinselectsbetweenlinearandinterleavedburst  
sequence.TheADV/LDsignalisusedtoloadanewexternaladdress(ADV/  
LD=LOW) orincrementtheinternalburstcounter(ADV/LD=HIGH).  
The IDT71V65602/5802 SRAM utilize IDT's latest high-performance  
256K x 36, 512K x 18 memory configurations  
Supports high performance system speed - 150MHz  
(3.8ns Clock-to-Data Access)  
ZBT Feature - No dead cycles between write and read cycles  
Internally synchronized output buffer enable eliminates the  
TM  
need to control OE  
Single R/W (READ/WRITE) control pin  
Positive clock-edge triggered address, data, and control  
signal registers for fully pipelined applications  
4-word burst capability (interleaved or linear)  
Individual byte write (BW1 - BW4) control (May tie active)  
Three chip enables for simple depth expansion  
3.3V power supply (±5%)  
2.5V I/O Supply (VDDQ)  
Power down controlled by ZZ input  
Packaged in a JEDEC standard 100-pin plastic thin quad and  
flatpack (TQFP), 119 ball grid array (BGA) and 165 fine pitch  
ball grid array (fBGA)  
Description  
The IDT71V65602/5802 are 3.3V high-speed 9,437,184-bit CMOSprocess,andarepackagedinaJEDECStandard14mmx20mm100-  
(9Megabit)synchronousSRAMs.Theyaredesignedtoeliminatedead pinthinplasticquadflatpack(TQFP)aswellasa119ballgridarray(BGA)  
bus cycles when turning the bus around between reads and writes, or and a 165 fine pitch ball grid array (fBGA).  
TM  
writes andreads.Thus,theyhavebeengiventhenameZBT ,orZero  
Bus Turnaround.  
PinDescriptionSummary  
A0-A18  
Address Inputs  
Input  
Input  
Input  
Input  
Input  
Input  
Input  
Input  
Input  
Input  
I/O  
Synchronous  
Synchronous  
Asynchronous  
Synchronous  
Synchronous  
Synchronous  
N/A  
Chip Enables  
CE1, CE2, CE2  
Output Enable  
OE  
R/W  
Read/Write Signal  
Clock Enable  
CEN  
Individual Byte Write Selects  
Clock  
BW1, BW2, BW3, BW4  
CLK  
ADV/LD  
Advance burstaddress / Load new address  
Linear / Interleaved Burst Order  
Sleep Mode  
Synchronous  
Static  
LBO  
ZZ  
Asynchronous  
Synchronous  
Static  
I/O0-I/O31, I/OP1-I/OP4  
VDD, VDDQ  
Data Input / Output  
Core Power, I/O Power  
Ground  
Supply  
Supply  
VSS  
Static  
5303 tbl 01  
ZBT and Zero Bus Turnaround are trademarks of Integrated Device Technology, Inc. and the architecture is supported by Micron Technology and Motorola, Inc.  
OCTOBER 2004  
1
©2004IntegratedDeviceTechnology,Inc.  
DSC-5303/05  

与71V65802S133PFG相关器件

型号 品牌 获取价格 描述 数据表
71V65802S133PFG8 IDT

获取价格

TQFP-100, Reel
71V65802S133PFGI IDT

获取价格

TQFP-100, Tray
71V65802S133PFGI8 IDT

获取价格

TQFP-100, Reel
71V65802S150BG8 IDT

获取价格

暂无描述
71V65802S150BGG IDT

获取价格

PBGA-119, Tray
71V65802S150BGG8 IDT

获取价格

PBGA-119, Reel
71V65802S150BQGI IDT

获取价格

ZBT SRAM, 512KX18, 3.8ns, CMOS, PBGA165, 13 X 15 MM, FPBGA-165
71V65802S150PFG8 IDT

获取价格

TQFP-100, Reel
71V65802S150PFGI8 IDT

获取价格

TQFP-100, Reel
71V65802Z100BG IDT

获取价格

ZBT SRAM, 512KX18, 5ns, CMOS, PBGA119, 14 X 22 MM, 1.27 MM PITCH, MS-028AA, BGA-119