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71V65802150BGI PDF预览

71V65802150BGI

更新时间： 2024-12-01 13:39:15
品牌 Logo 应用领域
艾迪悌 - IDT 时钟静态存储器内存集成电路
页数 文件大小 规格书
26页 489K
描述
ZBT SRAM, 512KX18, 3.8ns, CMOS, PBGA119, 14 X 22 MM, 1.27 MM PITCH, MS-028AA, BGA-119

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71V65802150BGI 技术参数

是否无铅：含铅是否Rohs认证：不符合
生命周期：Obsolete零件包装代码：BGA
包装说明：14 X 22 MM, 1.27 MM PITCH, MS-028AA, BGA-119针数：119
Reach Compliance Code：not_compliantECCN代码：3A991.B.2.A
HTS代码：8542.32.00.41风险等级：5.92
Is Samacsys：N最长访问时间：3.8 ns
其他特性：PIPELINED ARCHITECTURE最大时钟频率 (fCLK)：150 MHz
I/O 类型：COMMONJESD-30 代码：R-PBGA-B119
JESD-609代码：e0长度：22 mm
内存密度：9437184 bit内存集成电路类型：ZBT SRAM
内存宽度：18湿度敏感等级：3
功能数量：1端子数量：119
字数：524288 words字数代码：512000
工作模式：SYNCHRONOUS最高工作温度：85 °C
最低工作温度：-40 °C组织：512KX18
输出特性：3-STATE封装主体材料：PLASTIC/EPOXY
封装代码：BGA封装等效代码：BGA119,7X17,50
封装形状：RECTANGULAR封装形式：GRID ARRAY
并行/串行：PARALLEL峰值回流温度（摄氏度）：225
电源：2.5,3.3 V认证状态：Not Qualified
座面最大高度：2.36 mm最大待机电流：0.06 A
子类别：SRAMs最大压摆率：0.345 mA
最大供电电压 (Vsup)：3.465 V最小供电电压 (Vsup)：3.135 V
标称供电电压 (Vsup)：3.3 V表面贴装：YES
技术：CMOS温度等级：INDUSTRIAL
端子面层：Tin/Lead (Sn63Pb37)端子形式：BALL
端子节距：1.27 mm端子位置：BOTTOM
处于峰值回流温度下的最长时间：20宽度：14 mm
Base Number Matches：1

71V65802150BGI 数据手册

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256K x 36, 512K x 18  
IDT71V65602/Z  
IDT71V65802/Z  
3.3VSynchronousZBT™SRAMs  
2.5V I/O, Burst Counter  
PipelinedOutputs  
Features  
AddressandcontrolsignalsareappliedtotheSRAMduringoneclock  
cycle,andtwocycleslatertheassociateddatacycleoccurs,beitreadorwrite.  
The IDT71V65602/5802 contain data I/O, address and control signal  
registers.Outputenableistheonlyasynchronoussignalandcanbeusedto  
disabletheoutputsatanygiventime.  
A Clock Enable (CEN) pin allows operation of the IDT71V65602/5802  
tobesuspendedaslongasnecessary.Allsynchronousinputsareignored  
when(CEN)ishighandtheinternaldeviceregisterswillholdtheirprevious  
values.  
◆
256K x 36, 512K x 18 memory configurations  
◆
Supports high performance system speed - 150MHz  
(3.8ns Clock-to-Data Access)  
◆
ZBTTM Feature - No dead cycles between write and read cycles  
◆
Internally synchronized output buffer enable eliminates the  
need to control OE  
Single R/W (READ/WRITE) control pin  
Positive clock-edge triggered address, data, and control  
◆
◆
There are three chip enable pins (CE1, CE2, CE2) that allow the  
user to deselect the device when desired. If any one of these three are not  
asserted when ADV/LDis low, no new memory operation can be initiated.  
However,anypendingdatatransfers(readsorwrites)willbecompleted.The  
databuswilltri-statetwocyclesafterchipisdeselectedorawriteisinitiated.  
The IDT71V65602/5802 have an on-chip burst counter. In the burst  
mode, the IDT71V65602/5802 can provide four cycles of data for a single  
addresspresentedtotheSRAM.Theorderoftheburstsequenceisdefined  
bytheLBOinputpin.TheLBOpinselectsbetweenlinearandinterleavedburst  
sequence.TheADV/LDsignalisusedtoloadanewexternaladdress(ADV/  
LD=LOW) orincrementtheinternalburstcounter(ADV/LD=HIGH).  
The IDT71V65602/5802 SRAM utilize IDT's latest high-performance  
signal registers for fully pipelined applications  
4-word burst capability (interleaved or linear)  
Individual byte write (BW1 - BW4) control (May tie active)  
Three chip enables for simple depth expansion  
3.3V power supply (±5%)  
2.5V I/O Supply (VDDQ)  
Power down controlled by ZZ input  
Packaged in a JEDEC standard 100-pin plastic thin quad and  
◆
◆
◆
◆
◆
◆
◆
flatpack (TQFP), 119 ball grid array (BGA) and 165 fine pitch  
ball grid array (fBGA)  
Description  
The IDT71V65602/5802 are 3.3V high-speed 9,437,184-bit CMOSprocess,andarepackagedinaJEDECStandard14mmx20mm100-  
(9Megabit)synchronousSRAMs.Theyaredesignedtoeliminatedead  
bus cycles when turning the bus around between reads and writes, or  
writesandreads. Thus, theyhavebeengiventhenameZBTTM, orZero  
Bus Turnaround.  
pin thin plastic quad flatpack (TQFP) as well as a 119 ball grid array (BGA)  
and a 165 fine pitch ball grid array (fBGA).  
PinDescriptionSummary  
A
0
-A18  
Address Inputs  
Input  
Input  
Input  
Input  
Input  
Input  
Input  
Input  
Input  
Input  
I/O  
Synchronous  
Synchronous  
Asynchronous  
Synchronous  
Synchronous  
Synchronous  
N/A  
Chip Enables  
CE  
1, CE  
2
, CE  
2
Output Enable  
OE  
R/W  
Read/Write Signal  
Clock Enable  
CEN  
Individual Byte Write Selects  
Clock  
BW  
1, BW  
2
, BW  
3
, BW  
4
CLK  
ADV/LD  
Advance burst address / Load new address  
Linear / Interleaved Burst Order  
Sleep Mode  
Synchronous  
Static  
LBO  
ZZ  
Asynchronous  
Synchronous  
Static  
I/O  
0-I/O31, I/OP1-I/OP4  
Data Input / Output  
Core Power, I/O Power  
Ground  
V
V
DD, VDDQ  
SS  
Supply  
Supply  
Static  
5303 tbl 01  
ZBT and Zero Bus Turnaround are trademarks of Integrated Device Technology, Inc. and the architecture is supported by Micron Technology and Motorola, Inc.  
FEBRUARY 2009  
1
©2007IntegratedDeviceTechnology,Inc.  
DSC-5303/06  
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71V65802150PFI IDT

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71V65802S100BGG IDT

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 		PBGA-119, Tray
71V65802S100BGG8 IDT

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 		PBGA-119, Reel
71V65802S100BGGI IDT

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 		PBGA-119, Tray
71V65802S100BGGI8 IDT

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 		PBGA-119, Reel
71V65802S100BQ8 IDT

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 		CABGA-165, Reel
71V65802S100BQG IDT

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 		CABGA-165, Tray
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 		TQFP-100, Reel

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