Datasheet > 71V65802100PF

71V65802100PF

更新时间： 2024-12-01 13:39:15

品牌	Logo	应用领域
艾迪悌 - IDT		时钟静态存储器内存集成电路
页数	文件大小	规格书
26页	489K
描述
ZBT SRAM, 512KX18, 5ns, CMOS, PQFP100, 14 X 20 MM, 1.40 MM HEIGHT, 1 MM PITCH, PLASTIC, MO-136DJ, TQFP-100

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71V65802100PF 技术参数

是否无铅：	含铅	是否Rohs认证：	不符合
生命周期：	Obsolete	零件包装代码：	QFP
包装说明：	14 X 20 MM, 1.40 MM HEIGHT, 1 MM PITCH, PLASTIC, MO-136DJ, TQFP-100	针数：	100
Reach Compliance Code：	not_compliant	ECCN代码：	3A991.B.2.A
HTS代码：	8542.32.00.41	风险等级：	5.92
Is Samacsys：	N	最长访问时间：	5 ns
其他特性：	PIPELINED ARCHITECTURE	最大时钟频率 (fCLK)：	100 MHz
I/O 类型：	COMMON	JESD-30 代码：	R-PQFP-G100
JESD-609代码：	e0	长度：	20 mm
内存密度：	9437184 bit	内存集成电路类型：	ZBT SRAM
内存宽度：	18	湿度敏感等级：	3
功能数量：	1	端子数量：	100
字数：	524288 words	字数代码：	512000
工作模式：	SYNCHRONOUS	最高工作温度：	70 °C
最低工作温度：		组织：	512KX18
输出特性：	3-STATE	封装主体材料：	PLASTIC/EPOXY
封装代码：	LQFP	封装等效代码：	QFP100,.63X.87
封装形状：	RECTANGULAR	封装形式：	FLATPACK, LOW PROFILE
并行/串行：	PARALLEL	峰值回流温度（摄氏度）：	240
电源：	2.5,3.3 V	认证状态：	Not Qualified
座面最大高度：	1.6 mm	最大待机电流：	0.04 A
子类别：	SRAMs	最大压摆率：	0.25 mA
最大供电电压 (Vsup)：	3.465 V	最小供电电压 (Vsup)：	3.135 V
标称供电电压 (Vsup)：	3.3 V	表面贴装：	YES
技术：	CMOS	温度等级：	COMMERCIAL
端子面层：	Tin/Lead (Sn85Pb15)	端子形式：	GULL WING
端子节距：	0.65 mm	端子位置：	QUAD
处于峰值回流温度下的最长时间：	20	宽度：	14 mm
Base Number Matches：	1

71V65802100PF 数据手册

256K x 36, 512K x 18

IDT71V65602/Z

IDT71V65802/Z

3.3VSynchronousZBT™SRAMs

2.5V I/O, Burst Counter

PipelinedOutputs

Features

AddressandcontrolsignalsareappliedtotheSRAMduringoneclock

cycle,andtwocycleslatertheassociateddatacycleoccurs,beitreadorwrite.

The IDT71V65602/5802 contain data I/O, address and control signal

registers.Outputenableistheonlyasynchronoussignalandcanbeusedto

disabletheoutputsatanygiventime.

A Clock Enable (CEN) pin allows operation of the IDT71V65602/5802

tobesuspendedaslongasnecessary.Allsynchronousinputsareignored

when(CEN)ishighandtheinternaldeviceregisterswillholdtheirprevious

values.

◆

256K x 36, 512K x 18 memory configurations

◆

Supports high performance system speed - 150MHz

(3.8ns Clock-to-Data Access)

◆

ZBT^TMFeature - No dead cycles between write and read cycles

◆

Internally synchronized output buffer enable eliminates the

need to control OE

Single R/W (READ/WRITE) control pin

Positive clock-edge triggered address, data, and control

◆

There are three chip enable pins (CE¹, CE2, CE2) that allow the

user to deselect the device when desired. If any one of these three are not

asserted when ADV/LDis low, no new memory operation can be initiated.

However,anypendingdatatransfers(readsorwrites)willbecompleted.The

databuswilltri-statetwocyclesafterchipisdeselectedorawriteisinitiated.

The IDT71V65602/5802 have an on-chip burst counter. In the burst

mode, the IDT71V65602/5802 can provide four cycles of data for a single

addresspresentedtotheSRAM.Theorderoftheburstsequenceisdefined

bytheLBOinputpin.TheLBOpinselectsbetweenlinearandinterleavedburst

sequence.TheADV/LDsignalisusedtoloadanewexternaladdress(ADV/

LD=LOW) orincrementtheinternalburstcounter(ADV/LD=HIGH).

The IDT71V65602/5802 SRAM utilize IDT's latest high-performance

signal registers for fully pipelined applications

4-word burst capability (interleaved or linear)

Individual byte write (BW1 - BW4) control (May tie active)

Three chip enables for simple depth expansion

3.3V power supply (±5%)

2.5V I/O Supply (VDDQ)

Power down controlled by ZZ input

Packaged in a JEDEC standard 100-pin plastic thin quad and

◆

flatpack (TQFP), 119 ball grid array (BGA) and 165 fine pitch

ball grid array (fBGA)

Description

The IDT71V65602/5802 are 3.3V high-speed 9,437,184-bit CMOSprocess,andarepackagedinaJEDECStandard14mmx20mm100-

(9Megabit)synchronousSRAMs.Theyaredesignedtoeliminatedead

bus cycles when turning the bus around between reads and writes, or

writesandreads. Thus, theyhavebeengiventhenameZBT^TM, orZero

Bus Turnaround.

pin thin plastic quad flatpack (TQFP) as well as a 119 ball grid array (BGA)

and a 165 fine pitch ball grid array (fBGA).

PinDescriptionSummary

-A18

Address Inputs

Input

I/O

Synchronous

Asynchronous

Synchronous

N/A

Chip Enables

1, CE

, CE

Output Enable

R/W

Read/Write Signal

Clock Enable

CEN

Individual Byte Write Selects

Clock

1, BW

, BW

CLK

ADV/LD

Advance burst address / Load new address

Linear / Interleaved Burst Order

Sleep Mode

Synchronous

Static

LBO

Asynchronous

Synchronous

Static

I/O

0-I/O31, I/OP1-I/OP4

Data Input / Output

Core Power, I/O Power

Ground

DD, VDDQ

Supply

Static

5303 tbl 01

ZBT and Zero Bus Turnaround are trademarks of Integrated Device Technology, Inc. and the architecture is supported by Micron Technology and Motorola, Inc.

FEBRUARY 2009

DSC-5303/06

12 3 4 5 6 7...26

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与71V65802100PF相关器件

型号	品牌	获取价格	描述	数据表
71V65802100PFI	IDT	获取价格	ZBT SRAM, 512KX18, 5ns, CMOS, PQFP100, 14 X 20 MM, 1.40 MM HEIGHT, 1 MM PITCH, PLASTIC, MO
71V65802133BQ	IDT	获取价格	ZBT SRAM, 512KX18, 4.2ns, CMOS, PBGA165, 13 X 15 MM, 1.2 MM HEIGHT, FPBGA-165
71V65802133BQI	IDT	获取价格	ZBT SRAM, 512KX18, 4.2ns, CMOS, PBGA165, 13 X 15 MM, 1.2 MM HEIGHT, FPBGA-165
71V65802133PF	IDT	获取价格	ZBT SRAM, 512KX18, 4.2ns, CMOS, PQFP100, 14 X 20 MM, 1.40 MM HEIGHT, 1 MM PITCH, PLASTIC,
71V65802133PFI	IDT	获取价格	ZBT SRAM, 512KX18, 4.2ns, CMOS, PQFP100, 14 X 20 MM, 1.40 MM HEIGHT, 1 MM PITCH, PLASTIC,
71V65802150BGI	IDT	获取价格	ZBT SRAM, 512KX18, 3.8ns, CMOS, PBGA119, 14 X 22 MM, 1.27 MM PITCH, MS-028AA, BGA-119
71V65802150BQI	IDT	获取价格	ZBT SRAM, 512KX18, 3.8ns, CMOS, PBGA165, 13 X 15 MM, 1.2 MM HEIGHT, FPBGA-165
71V65802150PF	IDT	获取价格	ZBT SRAM, 512KX18, 3.8ns, CMOS, PQFP100, 14 X 20 MM, 1.40 MM HEIGHT, 1 MM PITCH, PLASTIC,
71V65802150PFI	IDT	获取价格	ZBT SRAM, 512KX18, 3.8ns, CMOS, PQFP100, 14 X 20 MM, 1.40 MM HEIGHT, 1 MM PITCH, PLASTIC,
71V65802S100BGG	IDT	获取价格	PBGA-119, Tray

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