Datasheet > 71V65703S75BQI

71V65703S75BQI

更新时间： 2024-11-08 20:36:55

品牌	Logo	应用领域
艾迪悌 - IDT		时钟静态存储器内存集成电路
页数	文件大小	规格书
26页	512K
描述
ZBT SRAM, 256KX36, 7.5ns, CMOS, PBGA165, 13 X 15 MM, 1.2 MM HEIGHT, 1 MM PITCH, FPBGA-165

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71V65703S75BQI 技术参数

是否无铅：	含铅	是否Rohs认证：	不符合
生命周期：	Active	零件包装代码：	BGA
包装说明：	TBGA, BGA165,11X15,40	针数：	165
Reach Compliance Code：	not_compliant	ECCN代码：	3A991.B.2.A
HTS代码：	8542.32.00.41	风险等级：	5.44
最长访问时间：	7.5 ns	其他特性：	FLOW-THROUGH ARCHITECTURE
最大时钟频率 (fCLK)：	100 MHz	I/O 类型：	COMMON
JESD-30 代码：	R-PBGA-B165	JESD-609代码：	e0
长度：	15 mm	内存密度：	9437184 bit
内存集成电路类型：	ZBT SRAM	内存宽度：	36
湿度敏感等级：	3	功能数量：	1
端子数量：	165	字数：	262144 words
字数代码：	256000	工作模式：	SYNCHRONOUS
最高工作温度：	85 °C	最低工作温度：	-40 °C
组织：	256KX36	输出特性：	3-STATE
封装主体材料：	PLASTIC/EPOXY	封装代码：	TBGA
封装等效代码：	BGA165,11X15,40	封装形状：	RECTANGULAR
封装形式：	GRID ARRAY, THIN PROFILE	并行/串行：	PARALLEL
峰值回流温度（摄氏度）：	225	电源：	3.3 V
认证状态：	Not Qualified	座面最大高度：	1.2 mm
最大待机电流：	0.06 A	最小待机电流：	3.14 V
子类别：	SRAMs	最大压摆率：	0.295 mA
最大供电电压 (Vsup)：	3.465 V	最小供电电压 (Vsup)：	3.135 V
标称供电电压 (Vsup)：	3.3 V	表面贴装：	YES
技术：	CMOS	温度等级：	INDUSTRIAL
端子面层：	Tin/Lead (Sn63Pb37)	端子形式：	BALL
端子节距：	1 mm	端子位置：	BOTTOM
处于峰值回流温度下的最长时间：	20	宽度：	13 mm
Base Number Matches：	1

71V65703S75BQI 数据手册

256K x 36, 512K x 18

IDT71V65703

IDT71V65903

3.3VSynchronousZBT™SRAMs

3.3V I/O, Burst Counter

Flow-Through Outputs

cycle,andonthenextclockcycletheassociateddatacycleoccurs,beit

read or write.

TheIDT71V65703/5903containaddress,data-inandcontrolsignal

registers.Theoutputsareflow-through(nooutputdataregister).Output

enable is the only asynchronous signal and can be used to disable the

outputsatanygiventime.

Features

◆

256K x 36, 512K x 18 memory configurations

◆

Supports high performance system speed - 100 MHz

(7.5 ns Clock-to-Data Access)

ZBT^TMFeature - No dead cycles between write and read

◆

cycles

◆

A Clock Enable (CEN) pin allows operation of the IDT71V65703/5903

tobesuspendedaslongasnecessary.Allsynchronousinputsareignoredwhen

CENishighandtheinternaldeviceregisterswillholdtheirpreviousvalues.

There are three chip enable pins (CE¹, CE2, CE2) that allow the

usertodeselectthedevicewhendesired.Ifanyoneofthesethreeisnot

assertedwhenADV/LDislow,nonewmemoryoperationcanbeinitiated.

However,anypendingdatatransfers(readsorwrites)willbecompleted.

Thedatabuswilltri-stateonecycleafterthechipisdeselectedorawrite

isinitiated.

TheIDT71V65703/5903haveanon-chipburstcounter.Intheburst

mode,theIDT71V65703/5903canprovidefourcyclesofdataforasingle

address presented to the SRAM. The order of the burst sequence is

defined by the LBO input pin. The LBO pin selects between linear and

interleaved burst sequence. The ADV/LD signal is used to load a new

externaladdress(ADV/LD=LOW)orincrementtheinternalburstcounter

(ADV/LD = HIGH).

Internally synchronized output buffer enable eliminates the

need to control OE

◆

Single R/W (READ/WRITE) control pin

◆

4-word burst capability (Interleaved or linear)

Individual byte write (BW¹- BW⁴) control (May tie active)

Three chip enables for simple depth expansion

3.3V power supply (±5%)

3.3V (±5%) I/O Supply (VDDQ)

Power down controlled by ZZ input

Packaged in a JEDEC standard 100-pin plastic thin quad

◆

flatpack (TQFP), 119 ball grid array (BGA) and 165 fine pitch

ball grid array (fBGA).

Description

The IDT71V65703/5903 are 3.3V high-speed 9,437,184-bit

(9 Megabit) synchronous SRAMs organized as 256K x 36 / 512K x 18.

They are designed to eliminate dead bus cycles when turning the bus

aroundbetweenreads andwrites,orwrites andreads.Thus theyhave

been given the name ZBT^TM, or Zero Bus Turnaround.

AddressandcontrolsignalsareappliedtotheSRAMduringoneclock

TheIDT71V65703/5903SRAMsutilizeIDT’slatesthigh-performance

CMOSprocessandarepackagedinaJEDECStandard14mmx20mm100-

pinplasticthinquadflatpack(TQFP), 119 ballgridarray(BGA)and a 165

fine pitchballgridarray(fBGA).

PinDescriptionSummary

A0-A18

Address Inputs

Input

I/O

Synchronous

Asynchronous

Synchronous

N/A

Chip Enables

CE1, CE2, CE2

Output Enable

R/W

Read/Write Signal

Clock Enable

CEN

Individual Byte Write Selects

Clock

BW1, BW2, BW3, BW4

CLK

ADV/LD

Advance Burst Address/Load New Address

Linear/Interleaved Burst Order

Sleep Mode

Synchronous

Static

LBO

Asynchronous

Synchronous

Static

I/ O0-I/O31, I/OP1-I/OP4

VDD, VDDQ

Data Input/Output

Core Power, I/O Power

Ground

Supply

VSS

Static

5298 tbl 01

ZBT and Zero Bus Turnaround are trademarks of Integrated Device Technology, Inc. and the architecture is supported by Micron Technology and Motorola, Inc.

FEBRUARY 2009

DECEMBER 2002

DSC-5298/03

12 3 4 5 6 7...26

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与71V65703S75BQI相关器件

型号	品牌	获取价格	描述	数据表
71V65703S75PFI	ROCHESTER	获取价格	256KX36 ZBT SRAM, 7.5ns, PQFP100, 14 X 20 MM, 1.40 MM HEIGHT, MO-136DJ, PLASTIC, TQFP-100
71V65802100BGI	IDT	获取价格	ZBT SRAM, 512KX18, 5ns, CMOS, PBGA119, 14 X 22 MM, 1.27 MM PITCH, MS-028AA, BGA-119
71V65802100BQ	IDT	获取价格	ZBT SRAM, 512KX18, 5ns, CMOS, PBGA165, 13 X 15 MM, 1.2 MM HEIGHT, FPBGA-165
71V65802100BQI	IDT	获取价格	ZBT SRAM, 512KX18, 5ns, CMOS, PBGA165, 13 X 15 MM, 1.2 MM HEIGHT, FPBGA-165
71V65802100PF	IDT	获取价格	ZBT SRAM, 512KX18, 5ns, CMOS, PQFP100, 14 X 20 MM, 1.40 MM HEIGHT, 1 MM PITCH, PLASTIC, MO
71V65802100PFI	IDT	获取价格	ZBT SRAM, 512KX18, 5ns, CMOS, PQFP100, 14 X 20 MM, 1.40 MM HEIGHT, 1 MM PITCH, PLASTIC, MO
71V65802133BQ	IDT	获取价格	ZBT SRAM, 512KX18, 4.2ns, CMOS, PBGA165, 13 X 15 MM, 1.2 MM HEIGHT, FPBGA-165
71V65802133BQI	IDT	获取价格	ZBT SRAM, 512KX18, 4.2ns, CMOS, PBGA165, 13 X 15 MM, 1.2 MM HEIGHT, FPBGA-165
71V65802133PF	IDT	获取价格	ZBT SRAM, 512KX18, 4.2ns, CMOS, PQFP100, 14 X 20 MM, 1.40 MM HEIGHT, 1 MM PITCH, PLASTIC,
71V65802133PFI	IDT	获取价格	ZBT SRAM, 512KX18, 4.2ns, CMOS, PQFP100, 14 X 20 MM, 1.40 MM HEIGHT, 1 MM PITCH, PLASTIC,

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