Datasheet > 71V65603Z150PFGI

71V65603Z150PFGI

更新时间： 2024-12-02 00:23:27

品牌	Logo	应用领域
艾迪悌 - IDT		静态存储器内存集成电路
页数	文件大小	规格书
26页	368K
描述
3.3V Synchronous ZBT SRAMs

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71V65603Z150PFGI 技术参数

是否Rohs认证：	符合	生命周期：	Active
包装说明：	LQFP,	Reach Compliance Code：	compliant
HTS代码：	8542.32.00.41	风险等级：	5.64
最长访问时间：	3.8 ns	其他特性：	PIPELINED ARCHITECTURE
JESD-30 代码：	R-PQFP-G100	长度：	20 mm
内存密度：	9437184 bit	内存集成电路类型：	ZBT SRAM
内存宽度：	36	功能数量：	1
端子数量：	100	字数：	262144 words
字数代码：	256000	工作模式：	SYNCHRONOUS
最高工作温度：	85 °C	最低工作温度：	-40 °C
组织：	256KX36	封装主体材料：	PLASTIC/EPOXY
封装代码：	LQFP	封装形状：	RECTANGULAR
封装形式：	FLATPACK, LOW PROFILE	并行/串行：	PARALLEL
峰值回流温度（摄氏度）：	260	座面最大高度：	1.6 mm
最大供电电压 (Vsup)：	3.465 V	最小供电电压 (Vsup)：	3.135 V
标称供电电压 (Vsup)：	3.3 V	表面贴装：	YES
技术：	CMOS	温度等级：	INDUSTRIAL
端子形式：	GULL WING	端子节距：	0.65 mm
端子位置：	QUAD	处于峰值回流温度下的最长时间：	30
宽度：	14 mm

71V65603Z150PFGI 数据手册

256K x 36, 512K x 18

3.3V Synchronous ZBT™ SRAMs

ZBT™ Feature

IDT71V65603/Z

IDT71V65803/Z

3.3V I/O, Burst Counter

Pipelined Outputs

AddressandcontrolsignalsareappliedtotheSRAMduringoneclock

cycle,andtwocycleslatertheassociateddatacycleoccurs,beitreadorwrite.

TheIDT71V65603/5803containdataI/O,addressandcontrolsignal

registers.Outputenableistheonlyasynchronoussignalandcanbeused

todisabletheoutputsatanygiventime.

A Clock Enable (CEN) pin allows operation of the IDT71V65603/5803

tobesuspendedaslongasnecessary.Allsynchronousinputsareignored

when(CEN)ishighandtheinternaldeviceregisterswillholdtheirprevious

values.

Therearethreechipenablepins(CE1, CE2, CE2)thatallowtheuser

to deselect the device when desired. If any one of these three are not

asserted when ADV/LD is low, no new memory operation can be

initiated. However, any pending data transfers (reads or writes) will be

completed. The data bus will tri-state two cycles after chip is deselected

or a write is initiated.

TheIDT71V65603/5803haveanon-chipburstcounter.Intheburst

mode, the IDT71V65603/5803 can provide four cycles of data for a

single address presented to the SRAM. The order of the burst

sequence is defined by the LBO input pin. The LBO pin selects

between linear and interleaved burst sequence. The ADV/LD signal is

used to load a new external address (ADV/LD = LOW) or increment

the internal burst counter (ADV/LD = HIGH).

Features

◆

256K x 36, 512K x 18 memory configurations

◆

Supports high performance system speed - 150MHz

(3.8ns Clock-to-Data Access)

◆

ZBT^TMFeature - No dead cycles between write and read cycles

◆

Internally synchronized output buffer enable eliminates the

need to control OE

Single R/W (READ/WRITE) control pin

Positive clock-edge triggered address, data, and control signal

◆

registers for fully pipelined applications

4-word burst capability (interleaved or linear)

Individual byte write (BW1 - BW4) control (May tie active)

Three chip enables for simple depth expansion

3.3V power supply (±5%)

3.3V I/O Supply (VDDQ)

Power down controlled by ZZ input

Packaged in a JEDEC standard 100-pin plastic thin quad

◆

flatpack (TQFP), 119 ball grid array (BGA) and 165 fine pitch

ball grid array(fBGA).

Description

The IDT71V65603/5803 are 3.3V high-speed 9,437,184-bit

(9Megabit)synchronousSRAMS.Theyaredesignedtoeliminatedeadbus

cycleswhenturningthebusaroundbetweenreadsandwrites, orwritesand

reads. Thus, they have been given the name ZBT^TM, or Zero Bus Turn-

around.

The IDT71V65603/5803 SRAM utilize IDT's latest high-performance

CMOS process, and are packaged in a JEDEC Standard 14mm x 20mm

100-pin thin plastic quad flatpack (TQFP) as well as a 119 ball grid array

(BGA) and 165 fine pitch ball grid array (fBGA) .

Pin Description Summary

0-A18

Address Inputs

Input

I/O

Synchronous

Asynchronous

Synchronous

N/A

Chip Enables

CE1

, CE

Output Enable

R/W

Read/Write Signal

Clock Enable

CEN

Individual Byte Write Selects

Clock

, BW

CLK

ADV/LD

LBO

Advance burst address / Load new address

Linear / Interleaved Burst Order

Sleep Mode

Synchronous

Static

Asynchronous

Synchronous

Static

I/O

-I/O31, I/OP1-I/OP4

Data Input / Output

Core Power, I/O Power

Ground

DD, VDDQ

Supply

Static

5304 tbl 01

ZBT and Zero Bus Turnaround are trademarks of Integrated Device Technology, Inc. and the architecture is supported by Micron Technology and Motorola, Inc.

OCTOBER 2008

DSC-5304/08

12 3 4 5 6 7...26

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与71V65603Z150PFGI相关器件

型号	品牌	获取价格	描述	数据表
71V65603ZS100PFG	IDT	获取价格	ZBT SRAM, 256KX36, 5ns, CMOS, PQFP100
71V65603ZS133BQG	IDT	获取价格	ZBT SRAM, 256KX36, 4.2ns, CMOS, PBGA165
71V65603ZS133BQGI	IDT	获取价格	ZBT SRAM, 256KX36, 4.2ns, CMOS, PBGA165
71V65603ZS133PF8	IDT	获取价格	ZBT SRAM, 256KX36, 4.2ns, CMOS, PQFP100
71V65603ZS150BGG	IDT	获取价格	ZBT SRAM, 256KX36, 3.8ns, CMOS, PBGA119
71V65603ZS150PFG	IDT	获取价格	ZBT SRAM, 256KX36, 3.8ns, CMOS, PQFP100
71V65703	RENESAS	获取价格	3.3V 256K x 36 ZBT Synchronous 3.3V I/O Flowthrough SRAM
71V65703S75BGGI8	IDT	获取价格	ZBT SRAM, 256KX36, 7.5ns, CMOS, PBGA119, 14 X 20 MM, 1.40 MM HEIGHT, GREEN, PLASTIC, MO-13
71V65703S75BQGI	IDT	获取价格	ZBT SRAM, 256KX36, 7.5ns, CMOS, PBGA165, 13 X 15 MM, FPBGA-165
71V65703S75BQGI8	IDT	获取价格	ZBT SRAM, 256KX36, 7.5ns, CMOS, PBGA165, 13 X 15 MM, GREEN, FPBGA-165

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