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5962-9760702MXC PDF预览

5962-9760702MXC

更新时间: 2024-02-11 11:05:39
品牌 Logo 应用领域
爱特美尔 - ATMEL 时钟ATM异步传输模式外围集成电路
页数 文件大小 规格书
83页 999K
描述
RISC Microprocessor, 32-Bit, 33MHz, CMOS, CPGA241, CERAMIC, PGA-241

5962-9760702MXC 技术参数

生命周期:Transferred包装说明:PGA, PGA241M,18X18
Reach Compliance Code:unknown风险等级:5.65
JESD-30 代码:S-XPGA-P241端子数量:241
最高工作温度:125 °C最低工作温度:-55 °C
封装主体材料:CERAMIC封装代码:PGA
封装等效代码:PGA241M,18X18封装形状:SQUARE
封装形式:GRID ARRAY电源:5 V
认证状态:Not Qualified筛选级别:38535Q/M;38534H;883B
子类别:Other Microprocessor ICs标称供电电压:5 V
表面贴装:NO温度等级:MILITARY
端子形式:PIN/PEG端子节距:2.54 mm
端子位置:PERPENDICULARBase Number Matches:1

5962-9760702MXC 数据手册

 浏览型号5962-9760702MXC的Datasheet PDF文件第4页浏览型号5962-9760702MXC的Datasheet PDF文件第5页浏览型号5962-9760702MXC的Datasheet PDF文件第6页浏览型号5962-9760702MXC的Datasheet PDF文件第8页浏览型号5962-9760702MXC的Datasheet PDF文件第9页浏览型号5962-9760702MXC的Datasheet PDF文件第10页 
TS68EN360  
Table 1. System Bus Signal Index (Normal Operation) (Continued)  
Group  
Signal Name  
Mnemonic  
Function  
Provides asynchronous data transfer acknowledgement and  
dynamic bus sizing (open-drain I/O but driven high before  
three-stated)  
Data and Size  
Acknowledge  
DSACK1 - DSACK0  
Address Strobe  
Data Strobe  
AS  
DS  
Indicates that a valid address is on the address bus. (I/O)  
During a read cycle, DS indicates that an external device  
should place valid data on the data bus. During a write cycle,  
DS indicates that valid data is on the data bus. (I/O)  
Bus Control  
Indicates the number of bytes remaining to be transferred for  
this cycle. (I/O)  
Size  
SIZ1-SIZ0  
R/W  
Read/Write  
Indicates the direction of data transfer on the bus. (I/O)  
Active during a read cycle indicates that an external device  
should place valid data on the data bus (O) or provides a  
strobe for external address multiplexing in DRAM accesses if  
internal multiplexing is not used. (O)  
Output Enable Address  
Multiplex  
OE/AMUX  
Interrupt Request  
Level 7-1  
Provides external interrupt requests to the CPU32+ at priority  
levels 7-1. (I)  
IRQ7-IRQ1  
Interrupt  
Control  
Autovector/Interrupt  
Acknowledge 5  
Autovector request during an interrupt acknowledge cycle  
(open-drain I/O) or interrupt level 5 acknowledge line. (O)  
AVEC/IACK5  
Soft Reset  
Hard Reset  
Halt  
RESETS  
RESETH  
HALT  
Soft system reset. (open-drain I/O)  
Hard system reset. (open-drain I/O)  
System  
Control  
Suspends external bus activity. (open-drain I/O)  
Indicates an erroneous bus operation is being attempted.  
(open-drain I/O)  
Bus Error  
BERR  
System Clock Out 1  
System Clock Out 2  
CLKO1  
CLKO2  
Internal system clock output 1. (O)  
Internal system clock output 2 - normally 2x CLKO1. (O)  
Connections for an external crystal to the internal oscillator  
circuit. EXTAL (I), XTAL (O)  
Crystal Oscillator  
EXTAL, XTAL  
XFC  
Connection pin for an external capacitor to filter the circuit of  
the PLL. (I)  
External Filter Capacitor  
Clock Mode Select 1-0  
Selects the source of the internal system clock. (I) THESE  
PINS SHOULD NOT BE SET TO 00  
MODCK1-MODCK0  
Indicates when the CPU32+ is performing an instruction word  
prefetch (O) or input to the CPU32+ background debug mode.  
(I)  
Instruction Fetch/  
Development Serial Input  
IFETCH/DSI  
IPIPE0/DSO  
Clock and Test  
Instruction Pipe 0/  
Development Serial  
Output  
Used to track movement of words through the instruction  
pipeline (O) or output from the CPU32+ background debug  
mode. (O)  
Instruction Pipe 1/Row  
Address Select 1  
Double-Drive  
Used to track movement of words through the instruction  
pipeline (O), or a row address select 1 “double-drive” output  
(O)  
IPIPE1/RAS1DD  
Breakpoint/Development  
Serial Clock  
Signals a hardware breakpoint to the QUICC (open-drain I/O),  
or clock signal for CPU32+ background debug mode (I)  
BKPT/DSCLK  
Freeze/Initial  
Configuration 2  
Indicates that the CPU32+ has acknowledged a breakpoint  
(O), or initial QUICC configuration select (I)  
FREEZE/CONFIG2  
7
2113B–HIREL–06/05  

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