TS68EN360
Table 1. System Bus Signal Index (Normal Operation) (Continued)
Group
Signal Name
Mnemonic
Function
Provides asynchronous data transfer acknowledgement and
dynamic bus sizing (open-drain I/O but driven high before
three-stated)
Data and Size
Acknowledge
DSACK1 - DSACK0
Address Strobe
Data Strobe
AS
DS
Indicates that a valid address is on the address bus. (I/O)
During a read cycle, DS indicates that an external device
should place valid data on the data bus. During a write cycle,
DS indicates that valid data is on the data bus. (I/O)
Bus Control
Indicates the number of bytes remaining to be transferred for
this cycle. (I/O)
Size
SIZ1-SIZ0
R/W
Read/Write
Indicates the direction of data transfer on the bus. (I/O)
Active during a read cycle indicates that an external device
should place valid data on the data bus (O) or provides a
strobe for external address multiplexing in DRAM accesses if
internal multiplexing is not used. (O)
Output Enable Address
Multiplex
OE/AMUX
Interrupt Request
Level 7-1
Provides external interrupt requests to the CPU32+ at priority
levels 7-1. (I)
IRQ7-IRQ1
Interrupt
Control
Autovector/Interrupt
Acknowledge 5
Autovector request during an interrupt acknowledge cycle
(open-drain I/O) or interrupt level 5 acknowledge line. (O)
AVEC/IACK5
Soft Reset
Hard Reset
Halt
RESETS
RESETH
HALT
Soft system reset. (open-drain I/O)
Hard system reset. (open-drain I/O)
System
Control
Suspends external bus activity. (open-drain I/O)
Indicates an erroneous bus operation is being attempted.
(open-drain I/O)
Bus Error
BERR
System Clock Out 1
System Clock Out 2
CLKO1
CLKO2
Internal system clock output 1. (O)
Internal system clock output 2 - normally 2x CLKO1. (O)
Connections for an external crystal to the internal oscillator
circuit. EXTAL (I), XTAL (O)
Crystal Oscillator
EXTAL, XTAL
XFC
Connection pin for an external capacitor to filter the circuit of
the PLL. (I)
External Filter Capacitor
Clock Mode Select 1-0
Selects the source of the internal system clock. (I) THESE
PINS SHOULD NOT BE SET TO 00
MODCK1-MODCK0
Indicates when the CPU32+ is performing an instruction word
prefetch (O) or input to the CPU32+ background debug mode.
(I)
Instruction Fetch/
Development Serial Input
IFETCH/DSI
IPIPE0/DSO
Clock and Test
Instruction Pipe 0/
Development Serial
Output
Used to track movement of words through the instruction
pipeline (O) or output from the CPU32+ background debug
mode. (O)
Instruction Pipe 1/Row
Address Select 1
Double-Drive
Used to track movement of words through the instruction
pipeline (O), or a row address select 1 “double-drive” output
(O)
IPIPE1/RAS1DD
Breakpoint/Development
Serial Clock
Signals a hardware breakpoint to the QUICC (open-drain I/O),
or clock signal for CPU32+ background debug mode (I)
BKPT/DSCLK
Freeze/Initial
Configuration 2
Indicates that the CPU32+ has acknowledged a breakpoint
(O), or initial QUICC configuration select (I)
FREEZE/CONFIG2
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2113B–HIREL–06/05