Datasheet > 5962-9760702MXC

5962-9760702MXC

更新时间： 2024-02-13 18:12:33

品牌	Logo	应用领域
爱特美尔 - ATMEL		时钟 ATM 异步传输模式外围集成电路
页数	文件大小	规格书
83页	999K
描述
RISC Microprocessor, 32-Bit, 33MHz, CMOS, CPGA241, CERAMIC, PGA-241

阅读下载

获取价格

技术参数
数据手册

如果您发现信息不准确，欢迎纠错

5962-9760702MXC 技术参数

生命周期：	Transferred	包装说明：	PGA, PGA241M,18X18
Reach Compliance Code：	unknown	风险等级：	5.65
JESD-30 代码：	S-XPGA-P241	端子数量：	241
最高工作温度：	125 °C	最低工作温度：	-55 °C
封装主体材料：	CERAMIC	封装代码：	PGA
封装等效代码：	PGA241M,18X18	封装形状：	SQUARE
封装形式：	GRID ARRAY	电源：	5 V
认证状态：	Not Qualified	筛选级别：	38535Q/M;38534H;883B
子类别：	Other Microprocessor ICs	标称供电电压：	5 V
表面贴装：	NO	温度等级：	MILITARY
端子形式：	PIN/PEG	端子节距：	2.54 mm
端子位置：	PERPENDICULAR	Base Number Matches：	1

5962-9760702MXC 数据手册

3.2

Signal Index

Table 1. System Bus Signal Index (Normal Operation)

Group

Signal Name

Mnemonic

Function

Address Bus

A27-A0

Lower 27 bits of address bus. (I/O)⁽¹⁾

Address Bus/Byte Write

Enables

A31-A28

WE3-WE0

Upper four bits of address bus (I/O), or byte write enable

signals (O)⁽¹⁾for accesses to external memory or peripherals.

Address

Identifies the processor state and the address space of the

current bus cycle. (I/O)

Function Codes

Data Bus 31 - 16

FC3-FC0

D31-D16

Upper 16-bit data bus used to transfer byte or word data.

Used in 16-bit bus mode. (I/O)

Data

Lower 16-bit data bus used to transfer 3-byte or long-word

data. (I/O)

Not used in 16-bit bus mode.

Data Bus 15 - 0

Parity 2 - 0

D15-D0

Parity signals for byte writes/reads from/to external memory

module. (I/O)

PRTY2-PRTY0

Parity

Parity signals for byte writes/reads from/to external memory

module or defines 16-bit bus mode. (I/O)

Parity 3/16BM

Parity Error

PRTY3/16BM

PERR

Indicates a parity error during a read cycle. (O)

Chip Select

Row Address Select 7

Interrupt Acknowledge 7

RAS7

IACK7

Enables peripherals or DRAMs at programmed addresses (O)

or interrupt level 7 acknowledge line. (O)

Memory

Controller

Chip Select 6-0

Row Address Select 6-0

CS6-CS0

RAS6-RAS0

Enables peripherals or DRAMs at programmed addresses.

(O)

Column Address Select

3 - 0/Interrupt

Acknowledge 1, 2, 3, 6

CAS3-CAS0/

IACK6,3,2,1

DRAM column address select or interrupt level acknowledge

lines. (O)

Indicates that an external device requires bus mastership.

(I)⁽¹⁾

Bus Request

Indicates that the current bus cycle is complete and the

QUICC has relinquished the bus. (O)

Bus Grant

Indicates that an external device has assumed bus

mastership. (I)

Bus Grand Acknowledge

BGACK

Bus Arbitration

Identifies the bus cycle as part of an indivisible

read-modify-write operation (I/O) or initial QUICC

configuration select. (I)

Read-Modify-Write Cycle

Initial Configuration 0

RMC

CONFIG0

Bus Clear Out/Initial

Configuration 1/Row

Address Select 2

Double-Drive

Indicates that an internal device requires the external bus

(Open-Drain O) or initial QUICC configuration select (I) or row

address select 2 double-drive output. (O)

BCLRO/CONFIG1/

RAS2DD

TS68EN360

2113B–HIREL–06/05

1...3 4 567 8 9...83

下载PDF

与5962-9760702MXC相关器件

型号	品牌	描述	获取价格	数据表
5962-9760702MYA	ATMEL	RISC Microprocessor, 32-Bit, 33MHz, CMOS, CQFP240, CERAMIC, LCC-240	获取价格
5962-9760801QXA	ETC	32-Bit Microprocessor	获取价格
5962-9760801QXX	WEDC	IC 32-BIT, 80 MHz, RISC PROCESSOR, CQFP240, CERAMIC, LCC-240, Microprocessor	获取价格
5962-9760802QXA	ETC	32-Bit Microprocessor	获取价格
5962-9760803QXA	ETC	32-Bit Microprocessor	获取价格
5962-9760804QXA	ETC	32-Bit Microprocessor	获取价格

与5962-9760702MXC相关文章

PCF8574资料解读：主要参数分析、引脚说明
2024-05-21

8
AD637数据手册解读：主要特性、引脚及其功能解读、电气参数
2024-05-21

8
ADUM1201资料手册解读：参数分析、引脚说明、应用分析
2024-05-21

11
一文带你了解压敏电阻器在直流电路中的过压保护作用
2024-05-21

6

产品中心

服务支持

精选活动

关于我们

帮助中心

5962-9760702MXC

5962-9760702MXC 技术参数

5962-9760702MXC 数据手册

与5962-9760702MXC相关器件

与5962-9760702MXC相关文章

您还可以找

产品中心

服务支持

精选活动

关于我们

帮助中心

5962-9760702MXC

5962-9760702MXC 技术参数

5962-9760702MXC 数据手册

与5962-9760702MXC相关器件

与5962-9760702MXC相关文章

您还可以找

您在本页遇到什么问题？