WF2M16-XXX5
HI-RELIABILITY PRODUCT
2Mx16 FLASH MODULE, SMD 5962-97610 PRELIMINARY*
FEATURES
■ Access Times of 90, 120, 150ns
■ Packaging:
■ Data Polling and Toggle Bit feature for detection of program
or erase cycle completion.
■ Supports reading or programming data to a sector not being
• 56 lead, Hermetic Ceramic, 0.520" CSOP (Package 207).
Fits standard 56 SSOP footprint.
erased.
■ Built-in Decoupling Caps and Multiple Ground Pins for Low
• 44 pin Ceramic SOJ (Package 102)**
Noise Operation.
• 44 lead Ceramic Flatpack (Package 208)**
■ Sector Architecture
■ RESET pin resets internal state machine to the read mode.
■ Ready/Busy (RY/BY) output for detection of program or
• 32 equal size sectors of 64KBytes each
• Any combination of sectors can be erased. Also supports
full chip erase.
erase cycle completion.
■ Multiple Ground Pins for Low Noise Operation
■ Minimum 100,000 Write/Erase Cycles Minimum
■ Organized as 2Mx16; User Configurable as 2 x 2Mx8
■ Commercial, Industrial, and Military Temperature Ranges
■ 5 Volt Read and Write. 5V ± 10% Supply.
■ Low Power CMOS
* This data sheet describes a product under development, not fully
characterized, and is subject to change without notice.
* * Package to be developed.
Note: For programming information refer to Flash Programming 16M5
Application Notes.
FIG. 1 PIN CONFIGURATIONS
PIN DESCRIPTION
WF2M16-XDAX5
56 CSOP
WF2M16-XXX5
44 CSOJ (DL)**
44 FLATPACK (FL)**
I/O0-15 Data Inputs/Outputs
TOP VIEW
A0-20
WE
Address Inputs
Write Enable
Chip Select
Output Enable
Power Supply
Ground
CS1
A12
A13
A14
A15
NC
1
2
3
4
5
6
7
8
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
TOP VIEW
NC
RESET
A11
A10
A9
A1
A2
A3
A4
A5
A6
A7
GND
A8
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
1
A15
A14
A16
A17
A18
A19
A20
OE
CS1-2
OE
2
3
A13
4
A12
CS2
NC
VCC
5
A11
6
A20
A19
A18
A17
A16
9
A10
VSS
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
7
A9
I/O7
I/O6
I/O5
I/O4
8
A8
RY/BY
RESET
Ready/Busy
Reset
9
RESET
CS1
10
11
12
13
14
15
16
17
18
19
20
21
22
V
CC
V
CC
VSS
GND
I/O6
I/O14
I/O7
I/O15
RY/BY
OE
WE
NC
I/O13
I/O5
I/O12
I/O4
V
CC
V
SS
V
CC
I/O9
I/O1
CS2
RY/BY
A7
I/O3
I/O2
I/O1
I/O0
WE
NC
BLOCK DIAGRAM
39 I/O8
38 I/O0
37 A0
36 NC
35 NC
34 NC
33 I/O2
32
31
30
29
I/O0-7
I/O8-15
A6
RESET
WE
A5
A4
OE
0-20
A
A3
NC
RY/BY
I/O10
I/O3
I/O11
GND
A2
NC
A1
NC
A0
NC
V
CC
2M x 8
2M x 8
** Package to be developed.
CS
CS
1
2
NOTE:
1. RY/BY is an open drain output and should be pulled up to Vcc
with an external resistor.
2. Address compatible with Intel 2M8 56 SSOP.
1
August 2001 Rev. 4
White Electronic Designs Corporation • (602) 437-1520 • www.whiteedc.com