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5962-9761601QDX PDF预览

5962-9761601QDX

更新时间: 2024-11-26 12:58:35
品牌 Logo 应用领域
德州仪器 - TI 触发器
页数 文件大小 规格书
19页 815K
描述
LVC/LCX/Z SERIES, DUAL POSITIVE EDGE TRIGGERED D FLIP-FLOP, COMPLEMENTARY OUTPUT, CDFP14, CERAMIC, DFP-14

5962-9761601QDX 技术参数

生命周期:Active零件包装代码:DFP
包装说明:CERAMIC, DFP-14针数:14
Reach Compliance Code:compliantHTS代码:8542.39.00.01
风险等级:5.21Is Samacsys:N
系列:LVC/LCX/ZJESD-30 代码:R-GDFP-F14
长度:9.21 mm负载电容(CL):50 pF
逻辑集成电路类型:D FLIP-FLOP最大频率@ Nom-Sup:100000000 Hz
最大I(ol):0.024 A位数:1
功能数量:2端子数量:14
最高工作温度:125 °C最低工作温度:-55 °C
输出极性:COMPLEMENTARY封装主体材料:CERAMIC, GLASS-SEALED
封装代码:DFP封装形状:RECTANGULAR
封装形式:FLATPACK峰值回流温度(摄氏度):NOT SPECIFIED
Prop。Delay @ Nom-Sup:6 ns传播延迟(tpd):6 ns
认证状态:Qualified筛选级别:MIL-PRF-38535 Class Q
座面最大高度:2.03 mm最大供电电压 (Vsup):3.6 V
最小供电电压 (Vsup):2 V标称供电电压 (Vsup):2.7 V
表面贴装:YES技术:CMOS
温度等级:MILITARY端子形式:FLAT
端子节距:1.27 mm端子位置:DUAL
处于峰值回流温度下的最长时间:NOT SPECIFIED触发器类型:POSITIVE EDGE
宽度:6.29 mm最小 fmax:100 MHz
Base Number Matches:1

5962-9761601QDX 数据手册

 浏览型号5962-9761601QDX的Datasheet PDF文件第2页浏览型号5962-9761601QDX的Datasheet PDF文件第3页浏览型号5962-9761601QDX的Datasheet PDF文件第4页浏览型号5962-9761601QDX的Datasheet PDF文件第5页浏览型号5962-9761601QDX的Datasheet PDF文件第6页浏览型号5962-9761601QDX的Datasheet PDF文件第7页 
SN54LVC74A, SN74LVC74A  
DUAL POSITIVE-EDGE-TRIGGERED D-TYPE FLIP-FLOPS  
WITH CLEAR AND PRESET  
www.ti.com  
SCAS287SJANUARY 1993REVISED MAY 2005  
FEATURES  
Latch-Up Performance Exceeds 250 mA Per  
JESD 17  
Operate From 1.65 V to 3.6 V  
Inputs Accept Voltages to 5.5 V  
Max tpd of 5.2 ns at 3.3 V  
ESD Protection Exceeds JESD 22  
– 2000-V Human-Body Model (A114-A)  
– 200-V Machine Model (A115-A)  
Typical VOLP (Output Ground Bounce)  
<0.8 V at VCC = 3.3 V, TA = 25°C  
– 1000-V Charged-Device Model (C101)  
Typical VOHV (Output VOH Undershoot)  
>2 V at VCC = 3.3 V, TA = 25°C  
SN54LVC74A . . . J OR W PACKAGE  
SN74LVC74A . . . D, DB, NS, OR PW PACKAGE  
(TOP VIEW)  
SN74LVC74A . . . RGY PACKAGE  
(TOP VIEW)  
SN54LVC74A . . . FK PACKAGE  
(TOP VIEW)  
1CLR  
1D  
V
CC  
1
2
3
4
5
6
7
14  
13  
12  
11  
10  
9
1
14  
2CLR  
2D  
3
2
1 20 19  
18  
1D  
1CLK  
1PRE  
1Q  
13 2CLR  
2
3
4
5
6
1CLK  
NC  
2D  
4
5
6
7
8
1CLK  
1PRE  
1Q  
12  
11  
10  
9
2D  
17  
16  
15  
14  
NC  
2CLK  
2PRE  
2Q  
2CLK  
2PRE  
2Q  
1PRE  
NC  
2CLK  
NC  
1Q  
1Q  
1Q  
2PRE  
8
GND  
2Q  
9 10 11 12 13  
7
8
NC - No internal connection  
DESCRIPTION/ORDERING INFORMATION  
The SN54LVC74A dual positive-edge-triggered D-type flip-flop is designed for 2.7-V to 3.6-V VCC operation, and  
the SN74LVC74A dual positive-edge-triggered D-type flip-flop is designed for 1.65-V to 3.6-V VCC operation.  
ORDERING INFORMATION  
TA  
PACKAGE(1)  
ORDERABLE PART NUMBER  
SN74LVC74ARGYR  
SN74LVC74AD  
TOP-SIDE MARKING  
LC74A  
QFN – RGY  
SOIC – D  
Reel of 1000  
Tube of 50  
Reel of 2500  
Reel of 250  
Reel of 2000  
Reel of 2000  
Tube of 90  
Reel of 2000  
Reel of 250  
Tube of 25  
Tube of 150  
Tube of 55  
SN74LVC74ADR  
LVC74A  
SN74LVC74ADT  
–40°C to 85°C  
SOP – NS  
SN74LVC74ANSR  
SN74LVC74ADBR  
SN74LVC74APW  
SN74LVC74APWR  
SN74LVC74APWT  
SNJ54LVC74AJ  
LCV74A  
LC74A  
SSOP – DB  
TSSOP – PW  
LC74A  
CDIP – J  
CFP – W  
LCCC – FK  
SNJ54LVC74AJ  
SNJ54LVC74AW  
SNJ54LVC74AFK  
–55°C to 125°C  
SNJ54LVC74AW  
SNJ54LVC74AFK  
(1) Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are available at  
www.ti.com/sc/package.  
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas  
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.  
PRODUCTION DATA information is current as of publication date.  
Copyright © 1993–2005, Texas Instruments Incorporated  
Products conform to specifications per the terms of the Texas  
On products compliant to MIL-PRF-38535, all parameters are  
Instruments standard warranty. Production processing does not  
tested unless otherwise noted. On all other products, production  
necessarily include testing of all parameters.  
processing does not necessarily include testing of all parameters.  

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