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5962-9760702MXC PDF预览

5962-9760702MXC

更新时间: 2024-01-21 22:56:02
品牌 Logo 应用领域
爱特美尔 - ATMEL 时钟ATM异步传输模式外围集成电路
页数 文件大小 规格书
83页 999K
描述
RISC Microprocessor, 32-Bit, 33MHz, CMOS, CPGA241, CERAMIC, PGA-241

5962-9760702MXC 技术参数

生命周期:Transferred包装说明:PGA, PGA241M,18X18
Reach Compliance Code:unknown风险等级:5.65
JESD-30 代码:S-XPGA-P241端子数量:241
最高工作温度:125 °C最低工作温度:-55 °C
封装主体材料:CERAMIC封装代码:PGA
封装等效代码:PGA241M,18X18封装形状:SQUARE
封装形式:GRID ARRAY电源:5 V
认证状态:Not Qualified筛选级别:38535Q/M;38534H;883B
子类别:Other Microprocessor ICs标称供电电压:5 V
表面贴装:NO温度等级:MILITARY
端子形式:PIN/PEG端子节距:2.54 mm
端子位置:PERPENDICULARBase Number Matches:1

5962-9760702MXC 数据手册

 浏览型号5962-9760702MXC的Datasheet PDF文件第6页浏览型号5962-9760702MXC的Datasheet PDF文件第7页浏览型号5962-9760702MXC的Datasheet PDF文件第8页浏览型号5962-9760702MXC的Datasheet PDF文件第10页浏览型号5962-9760702MXC的Datasheet PDF文件第11页浏览型号5962-9760702MXC的Datasheet PDF文件第12页 
TS68EN360  
Table 3-1.  
Group  
Peripherals Signal Index  
Signal Name  
Mnemonic  
RXD4-RXD1  
TXD4-TXD1  
Function  
Receive Data  
Serial receive data input to the SCCs. (I)  
Transmit Data  
Serial transmit data output from the SCCs. (O)  
Request to send outputs indicate that the SCC is ready to  
transmit data. (O)  
Request to Send  
Clear to Send  
Carrier Detect  
RTS4-RTS1  
CTS4-CTS1  
CD4-CD1  
Clear to send inputs indicate to the SCC that data  
transmission may begin. (I)  
Carrier detect inputs indicate that the SCC should begin  
reception of data. (I)  
SCC  
This output from SCC1 identifies the start of a receive frame.  
Can be used by an Ethernet CAM to perform address  
matching. (O)  
Receive Start  
RSTRT1  
RRJCT1  
This input to SCC1 allows a CAM to reject the current  
Ethernet frame after it determines the frame address did not  
match. (I)  
Receive Reject  
Input clocks to the SCCs, SCMs, SI, and the baud rate  
generators. (I)  
Clocks  
CLK8-CLK1  
DREQ2-DREQ1  
DACK2-DACK1  
DONE2-DONE1  
TGATE2-TGATE1  
TIN4-TIN1  
A request (input) to an IDMA channel to start an IDMA  
transfer. (I)  
DMA Request  
DMA Acknowledge  
DMA Done  
An acknowledgement (output) by the IDMA that an IDMA  
transfer is in progress. (O)  
IDMA  
A bidirectional signal that indicates the last IDMA transfer in  
a block of data. (I/O)  
An input to a timer that enables/disables the counting  
function. (I)  
Timer Gate  
Time reference input to the timer that allows it to function as  
a counter. (I)  
TIMER  
Timer Input  
Output waveform (pulse or toggle) from the timer as a result  
of a reference value being reached. (O)  
Timer Output  
SPI Master In Slave Out  
SPI Master Out Slave In  
SPI Clock  
TOUT4-TOUT1  
SPIMISO  
Serial data input to the SPI master (I); serial data output from  
an SPI slave. (O)  
Serial data output from the SPI master (O); serial data input  
to an SPI slave. (I)  
SPIMOSI  
SPI  
Output clock from the SPI master (O); input clock to the SPI  
slave. (I)  
SPICLK  
SPI Select  
SPISEL  
SPI slave select input. (I)  
SMC Receive Data  
SMC Transmit Data  
SMC Sync  
SMRXD2-SMRXD1  
SMTXD2-SMTXD1  
SMSYN2-SMSYN1  
Serial data input to the SMCs. (I)  
Serial data output from the SMCs. (O)  
SMC synchronization signal. (I)  
SMC  
9
2113B–HIREL–06/05  

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