Datasheet > 5962-9760702MXC

5962-9760702MXC

更新时间： 2024-02-13 11:09:32

品牌	Logo	应用领域
爱特美尔 - ATMEL		时钟 ATM 异步传输模式外围集成电路
页数	文件大小	规格书
83页	999K
描述
RISC Microprocessor, 32-Bit, 33MHz, CMOS, CPGA241, CERAMIC, PGA-241

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技术参数
数据手册

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5962-9760702MXC 技术参数

生命周期：	Transferred	包装说明：	PGA, PGA241M,18X18
Reach Compliance Code：	unknown	风险等级：	5.65
JESD-30 代码：	S-XPGA-P241	端子数量：	241
最高工作温度：	125 °C	最低工作温度：	-55 °C
封装主体材料：	CERAMIC	封装代码：	PGA
封装等效代码：	PGA241M,18X18	封装形状：	SQUARE
封装形式：	GRID ARRAY	电源：	5 V
认证状态：	Not Qualified	筛选级别：	38535Q/M;38534H;883B
子类别：	Other Microprocessor ICs	标称供电电压：	5 V
表面贴装：	NO	温度等级：	MILITARY
端子形式：	PIN/PEG	端子节距：	2.54 mm
端子位置：	PERPENDICULAR	Base Number Matches：	1

5962-9760702MXC 数据手册

Table 3-1.

Group

Peripherals Signal Index (Continued)

Signal Name

Mnemonic

Function

Serial input to the time division multiplexed (TDM) channel A

or channel B

SI Receive Data

L1RXDA, L1RXDB

L1TXDA, L1TXDB

SI Transmit Data

SI Receive Clock

SI Transmit Clock

Serial output from the TDM channel A or channel B

L1RCLKA, L1RCLKB Input receive clock to TDM channel A or channel B

L1TCLKA, L1TCLKB

Input transmit clock to TDM channel A or channel B

L1TSYNCA,

L1TSYNCB

Input transmit data sync signal to TDM channel A or

channel B

SI Transmit Sync Signals

SI Receive Sync Signals

IDL Interface Request

SI Output Clock

L1RSYNCA,

L1RSYNCB

Input receive data sync signal to TDM channel A or

channel B

IDL interface request to transmit on the D channel. Output

from the SI

L1RQA, L1RQB

Output serial data rate clock. Can output a data rate clock

when the input clock is 2x the data rate

L1CLKOA, L1CLKOB

Serial data strobe outputs can be used to gate clocks to

external devices that do not have a built-in time slot assigner

(TSA)

SI Data Strobes

L1ST4-L1ST1

Baud Rate Generator

Out 4-1

Baud rate generator output clock allows baud rate generator

to be used externally

BRGO4-BRGO1

BRG

Baud rate generator input clock from which BRG will derive

the baud rates

BRG Input Clock

Port B 15-0

CLK2, CLK6

PB15-BP0

STRBO

PIP Data I/O Pins

This input causes the PIP output data to be placed on the

PIP data pins

Strobe Out

PIP

This input causes data on the PIP data pins to be latched by

the PIP as input data

Strobe In

STRBI

SDMA output signals used in RISC receiver to mark fields in

the Ethernet receive frame

SDMA

SDMA Acknowledge 2-1

SDACK2-SDACK1

TS68EN360

2113B–HIREL–06/05

1...7 8 91011 12 13...83

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