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2N7002FN3 PDF预览

2N7002FN3

更新时间: 2024-11-18 07:29:15
品牌 Logo 应用领域
强茂 - PANJIT 晶体晶体管开关
页数 文件大小 规格书
3页 91K
描述
60V N-CHANNEL ENHANCEMENT MODE MOSFET

2N7002FN3 技术参数

是否无铅:不含铅是否Rohs认证:符合
生命周期:Active零件包装代码:DFN
包装说明:CHIP CARRIER, R-PBCC-N3针数:3
Reach Compliance Code:compliantECCN代码:EAR99
HTS代码:8541.21.00.95风险等级:5.55
Is Samacsys:N其他特性:ULTRA-LOW RESISTANCE
外壳连接:DRAIN配置:SINGLE WITH BUILT-IN DIODE
最小漏源击穿电压:60 V最大漏极电流 (ID):0.115 A
最大漏源导通电阻:5 ΩFET 技术:METAL-OXIDE SEMICONDUCTOR
最大反馈电容 (Crss):5 pFJESD-30 代码:R-PBCC-N3
元件数量:1端子数量:3
工作模式:ENHANCEMENT MODE封装主体材料:PLASTIC/EPOXY
封装形状:RECTANGULAR封装形式:CHIP CARRIER
峰值回流温度(摄氏度):NOT SPECIFIED极性/信道类型:N-CHANNEL
认证状态:Not Qualified表面贴装:YES
端子形式:NO LEAD端子位置:BOTTOM
处于峰值回流温度下的最长时间:NOT SPECIFIED晶体管应用:SWITCHING
晶体管元件材料:SILICONBase Number Matches:1

2N7002FN3 数据手册

 浏览型号2N7002FN3的Datasheet PDF文件第2页浏览型号2N7002FN3的Datasheet PDF文件第3页 
2N7002FN3  
60V N-CHANNEL ENHANCEMENT MODE MOSFET  
DFN 3L  
Unit : inch(mm))  
FEATURES  
0.042(1.05)  
0.037(0.95)  
• RDS(ON), VGS@10V,IDS@500mA=5Ω  
• RDS(ON), VGS@4.5V,IDS@50mA=7.5Ω  
• Advanced Trench Process Technology  
• High Density Cell Design For Ultra Low On-Resistance  
• Specially Designed for Battery Operated Systems, Solid-State  
Relays Drivers : Relays, Displays, Lamps, Solenoids, Memories, etc.  
• In compliance with EU RoHS 2002/95/EC directives  
0.002(0.05) MAX.  
0.013(0.32)  
0.008(0.22)  
0.013(0.32)  
0.008(0.22)  
0.014(0.36)  
MECHANICAL DATA  
• Case: DFN 3L, Plastic  
Terminals: Solderable per MIL-STD-750, Method 2026  
• Marking: AH  
2
3
1
Maximum Ratings and Thermal Characteristics (TA=25OC unless otherwise noted )  
PARAMETER  
SYMBOL  
LIMIT  
60  
UNITS  
Drain-Source Voltage  
Gats-Source Voltage  
Continous Drain Current  
Pulsed Drain Current (1)  
V
V
I
DS  
GS  
D
V
V
+20  
115  
800  
mA  
mA  
I
DM  
Maximum Power Dissipation  
P
D
150  
mW  
Junction-to Ambient Thermal Resistance (PCB mounted)2  
RθJA  
883  
oC/W  
oC  
Operating Junction and Storage Temperature Range  
T
J
,TSTG  
-55 to +150  
Note 1 : Maximum DC current limited by the package  
2 : Surface mounted on FR4 board,t<10 sec  
PAN JIT RESERVES THE RIGHT TO IMPROVE PRODUCT DSEIGN, FUNCTIONS AND RELIABILITY WITHOUT NOTICE  
September 03.2010-REV.00  
PAGE . 1  

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