ZVP4105ASMTA

更新时间： 2024-01-26 02:56:24

品牌	Logo	应用领域
美台 - DIODES		晶体小信号场效应晶体管
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数据手册

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ZVP4105ASMTA 数据手册

P-CHANNEL ENHANCEMENT

MODE VERTICAL DMOS FET

ISSUE 2 MARCH 94

ZVP4105A

FEATURES

50 Volt V_DS

R_DS(on)=10Ω

Low threshold

E-Line

TO92 Compatible

ABSOLUTE MAXIMUM RATINGS.

PARAMETER

SYMBOL

V_DS

VALUE

UNIT

Drain-Source Voltage

-50

-175

Continuous Drain Current at T_amb=25°C

Pulsed Drain Current

I_D

I_DM

-520

Gate Source Voltage

V_GS

± 20

Power Dissipation at T_amb=25°C

Operating and Storage Temperature Range

P_tot

625

°C

T_j:T_stg

-55 to +150

ELECTRICAL CHARACTERISTICS (at T

= 25°C unless otherwise stated).

amb

SYMBOL MIN. MAX. UNIT CONDITIONS.

PARAMETER

Drain-Source Breakdown

Voltage

BV_DSS

-50

I_D=-0.25mA, V_GS=0V

ID=-1mA, V_DS= V_GS

V_GS=± 20V, V_DS=0V

Gate-Source Threshold

Voltage

V_GS(th)

-0.8

-2.0

Gate-Body Leakage

I_GSS

I_DSS

Zero Gate Voltage Drain

Current

-15

-60

-100

V_DS=-50V, V_GS=0V

µA

V_DS=-50V, V_GS=0V, T=125°C(2)

V_DS=-25V, V_GS=0V

Static Drain-Source On-State R_DS(on)

Resistance (1)

V_GS=-5V,I_D=-100mA

Ω

Forward Transconductance

(1)(2)

g_fs

V_DS=-25V,I_D=-100mA

Input Capacitance (2)(4)

C_iss

Common Source Output

Capacitance (2)(4)

C_oss

V_DS=-25V, V_GS=0V, f=1MHz

Reverse Transfer

Capacitance (2)(4)

C_rss

Turn-On Delay Time (2)(3)(4) t_d(on)

Rise Time (2)(3)(4) t_r

Turn-Off Delay Time (2)(3)(4) t_d(off)

Fall Time (2)(3)(4) t_f

V_DD≈-30V, I_D=-270mA

(1) Measured under pulsed conditions. Width=300µs. Duty cycle ≤2%

(2) Sample test.

(3) Switching times measured with 50Ω source impedance and <5ns rise time on a pulse generator

(

)

3-435

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