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ZL40241LDF1 PDF预览

ZL40241LDF1

更新时间: 2024-11-29 19:56:47
品牌 Logo 应用领域
美高森美 - MICROSEMI 驱动逻辑集成电路
页数 文件大小 规格书
23页 764K
描述
Low Skew Clock Driver,

ZL40241LDF1 技术参数

生命周期:Active包装说明:HVQCCN,
Reach Compliance Code:compliantHTS代码:8542.39.00.01
风险等级:5.76其他特性:ALSO OPERATES AT 3.3 V SUPPLY
系列:4000/14000/40000输入调节:DIFFERENTIAL MUX
JESD-30 代码:S-XQCC-N32长度:5 mm
逻辑集成电路类型:LOW SKEW CLOCK DRIVER功能数量:1
反相输出次数:端子数量:32
实输出次数:10最高工作温度:85 °C
最低工作温度:-40 °C封装主体材料:UNSPECIFIED
封装代码:HVQCCN封装形状:SQUARE
封装形式:CHIP CARRIER, HEAT SINK/SLUG, VERY THIN PROFILE传播延迟(tpd):2.77 ns
Same Edge Skew-Max(tskwd):0.027 ns座面最大高度:1 mm
最大供电电压 (Vsup):2.625 V最小供电电压 (Vsup):2.375 V
标称供电电压 (Vsup):2.5 V表面贴装:YES
技术:CMOS温度等级:INDUSTRIAL
端子形式:NO LEAD端子节距:0.5 mm
端子位置:QUAD宽度:5 mm
最小 fmax:200 MHzBase Number Matches:1

ZL40241LDF1 数据手册

 浏览型号ZL40241LDF1的Datasheet PDF文件第2页浏览型号ZL40241LDF1的Datasheet PDF文件第3页浏览型号ZL40241LDF1的Datasheet PDF文件第4页浏览型号ZL40241LDF1的Datasheet PDF文件第5页浏览型号ZL40241LDF1的Datasheet PDF文件第6页浏览型号ZL40241LDF1的Datasheet PDF文件第7页 
Data Sheet  
ZL40241  
Ten LVCMOS Output Low Additive Jitter Fanout Buffer  
Ordering Information  
Features  
ZL40241LDG1  
ZL40241LDF1  
32 Pin QFN  
32 pin QFN  
Trays  
Tape and Reel  
3 to 1 input Multiplexer: Two inputs accept any  
differential (LVPECL, HCSL, LVDS, SSTL, CML,  
LVCMOS) or a single ended signal and the third  
input accepts a crystal or a single ended signal  
Package size: 5 x 5 mm  
-40 C to +85 C  
Ten 1.5V/1.8V/2.5V/3.3V LVCMOS outputs  
Supports frequencies from 0 to 200MHz  
Supports crystals from 8MHz to 60MHz  
Ultra-low additive jitter: 17fs (12kHz to 20MHz)  
Ultra-low noise floor of -170dBc/Hz  
Applications  
General purpose clock distribution  
Low jitter clock trees  
Logic translation  
Clock and data signal restoration  
Wired and Wireless communications  
High performance microprocessor clock distribution  
Medical Imaging  
Supports 2.5V or 3.3V power supplies  
Output to output skew of 30ps (typical)  
Input to output delay of 2ns (typical)  
Test equipment  
ZL40241  
OUT0  
Synchronous OE  
OE  
OUT1  
OUT2  
OUT3  
OUT4  
OUT5  
OUT6  
OUT7  
OUT8  
OUT9  
SEL0  
SEL1  
IN0_p  
IN0_n  
00  
IN1_p  
IN1_n  
01  
10  
11  
XOUT  
XIN  
Figure 1. Functional Block Diagram  
ZL40241  
Confidential  
1
February 2017  
© 2017 Microsemi Corporation  
 
 

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