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ZL40264LDG1 PDF预览

ZL40264LDG1

更新时间: 2024-11-29 20:55:51
品牌 Logo 应用领域
美国微芯 - MICROCHIP /
页数 文件大小 规格书
26页 916K
描述
Clock Driver

ZL40264LDG1 技术参数

生命周期:Active包装说明:HQCCN, LCC20,.16SQ,20
Reach Compliance Code:compliantFactory Lead Time:8 weeks
风险等级:1.74输入调节:DIFFERENTIAL
JESD-30 代码:S-PQCC-N20长度:4 mm
功能数量:1端子数量:20
实输出次数:4最高工作温度:85 °C
最低工作温度:-40 °C封装主体材料:PLASTIC/EPOXY
封装代码:HQCCN封装等效代码:LCC20,.16SQ,20
封装形状:SQUARE封装形式:CHIP CARRIER, HEAT SINK/SLUG, VERY THIN PROFILE
包装方法:TRAY最大电源电流(ICC):53 mA
Prop。Delay @ Nom-Sup:0.84 ns传播延迟(tpd):1 ns
Same Edge Skew-Max(tskwd):0.05 ns座面最大高度:1 mm
最大供电电压 (Vsup):2.625 V最小供电电压 (Vsup):2.375 V
标称供电电压 (Vsup):2.5 V表面贴装:YES
技术:CMOS温度等级:INDUSTRIAL
端子形式:NO LEAD端子节距:0.5 mm
端子位置:QUAD宽度:4 mm
最小 fmax:400 MHzBase Number Matches:1

ZL40264LDG1 数据手册

 浏览型号ZL40264LDG1的Datasheet PDF文件第2页浏览型号ZL40264LDG1的Datasheet PDF文件第3页浏览型号ZL40264LDG1的Datasheet PDF文件第4页浏览型号ZL40264LDG1的Datasheet PDF文件第5页浏览型号ZL40264LDG1的Datasheet PDF文件第6页浏览型号ZL40264LDG1的Datasheet PDF文件第7页 
Data Sheet  
ZL40264  
Four output ultra-low additive phase noise PCIe Gen 1 to 5,  
and UPI/QPI fanout buffer  
Ordering Information  
Features  
ZL40264LDG1  
ZL40264LDF1  
20 pin QFN  
20 pin QFN  
Trays  
Tape and Reel  
One differential input which accepts any  
differential format.  
Package size: 4 x 4 mm  
Four differential HCSL outputs  
-40 C to +85 C  
Ultra-low additive jitter: 32fs (in 12kHz to 20MHz  
integration band at 400MHz clock frequency)  
Applications  
Supports clock frequencies from 0 to 400MHz  
PCI Express generation 1/2/3/4/5 clock distribution  
UPI/QPI clock distribution  
Supports 2.5V or 3.3V power supplies for HCSL  
outputs  
Low jitter clock trees  
Embedded Low Drop Out (LDO) Voltage regulator  
Logic translation  
provides superior Power Supply Noise Rejection  
Clock and data signal restoration  
High performance microprocessor clock distribution  
Test Equipment  
Maximum output to output skew of 50ps  
Individual Output Enable pin for each differential  
pair.  
Transfers Spread-Spectrum without attenuation  
OE[3:0]_b  
OUT0_p  
OUT0_n  
OUT1_p  
OUT1_n  
IN_p  
IN_n  
OUT2_p  
OUT2_n  
ZL40264  
OUT3_p  
OUT3_n  
Figure 1. Functional Block Diagram  
ZL40264  
June 2019  
1
© 2019 Microsemi Corporation  
 
 
 

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